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參數(shù)資料
| 型號(hào)： | MULTILYNX |
| 英文描述： | MultiLynx CL2151 Universal HFC? Interactive Cable Transceiver |
| 中文描述： | MultiLynx CL2151通用光纖？交互式有線電視收發(fā)器 |
| 文件頁(yè)數(shù)： | 26/52頁(yè) |
| 文件大?。?/td> | 517K |
| 代理商： | MULTILYNX |
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26
MON08 Multilink User Manual
P&E
Microcomputer
Systems, Inc.
MON08 MULTILINK
3.23
68HC908QT
Figure 3-23: 68HC908QT Family MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
The user must pull up the RESET line to target VDD with an external resistor.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 8, acting as the communications line. The MON08 MULTILINK pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTA1 and PORTA4 are used for entering monitor mode. By default the user
may directly bring these signals out to the target MON08 Header.
Alternatively, the user may pull up PORTA1 and pull down PORTA4. In which
case the user does not need to connect these signals to the target MON08
Header. The clock division is fixed Div 4.
Please note that the MON08 MULTILINK will calculate the proper trim value
for the device being programmed and program this trim value to $FFC0.
3.24
68HC908QY
Figure 3-24: 68HC908QY Family MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
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