參數(shù)資料
型號(hào): MVTX2603AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA553
封裝: 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553
文件頁(yè)數(shù): 86/109頁(yè)
文件大小: 803K
代理商: MVTX2603AG
MVTX2603
Data Sheet
86
Zarlink Semiconductor Inc.
Note:
# = Active low signal
Input = Input signal
In-ST = Input signal with Schmitt-Trigger
Output = Output signal (Tri-State driver)
Out-OD = Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD = Input & Output signal with Open-Drain driver
14.3 Ball – Signal Name
AD29, AG28, AJ26, AE26,
AJ24, AE23, AJ22, AJ20,
AE20, AJ18, AJ21, AJ16,
AJ14, AE14, AJ12, AE11,
AJ10, AJ8, AE8, AJ6, AE5,
AJ4, AG1, AE1,
M[23:0]_TXEN
Default: RMII
0 – GPSI
1 - RMII
C21
P_D
Must be pulled-down
Reserved. Must be pulled-down.
C19, B19, A19
OE_CLK[2:0]
Default: 111
Programmable delay for internal
OE_CLK from SCLK input. The
OE_CLK is used for generating the
OE0 and OE1 signals
Suggested value is 001.
C20, B20, A20
LA_CLK[2:0]
Default: 111
Programmable delay for LA_CLK and
LB_CLK from internal OE_CLK. The
LA_CLK and LB_CLK delay from
SCLK is the sum of the delay
programmed in here and the delay in
P_D[15:13].
Suggested value is 011.
B22, A22, C23, B23, A23,
C24
MIRROR[5:0]
Default: 111111
Dedicated Port Mirror Mode. The first
5 bits select the port to be mirrored.
The last bit selects either ingress or
egress data.
Ball – Signal Name Table
Ball
No.
Signal
Name
Ball
No.
Signal Name
Ball No.
Signal
Name
D20
LA_D[63]
D3
LA_D[19]
A9
LA_OE0#
B21
LA_D[62]
E3
LA_D[18]
B9
LA_OE1#
D19
LA_D[61]
D2
LA_D[17]
F4
LB_D[63]
E19
LA_D[60]
E2
LA_D[16]
F5
LB_D[62]
D18
LA_D[59]
A7
LA_D[15]
G4
LB_D[61]
E18
LA_D[58]
B7
LA_D[14]
G5
LB_D[60]
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
I/O
Description
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