參數(shù)資料
型號： MVTX2802AG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 網(wǎng)絡接口
英文描述： Managed 4-Port 1000 Mbps Ethernet Switch
中文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝： 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù)： 18/154頁
文件大小： 1936K
代理商： MVTX2802AG
MVTX2802
Data Sheet
18
Zarlink Semiconductor Inc.
Note:
Deleting IP Multicast address requests by the MVTX2802AG occur when the CPU issues a Learn IP
Multicast address command but the search engine discovers no RAM space for storage.
The format of the Control Frame is described in the processor interface application note.
2.4 Unmanaged Mode
In unmanaged mode, the MVTX2802AG can be configured by EEPROM (24C02 or compatible) via an I
2
C
interface at boot time, or via a synchronous serial interface during operation. When the bootstrap Td[8] is set to
‘0’ meaning EEPROM installed, the MVTX2802, acting as a master starts the data transfer from the memory to
the switch.
2.5 I
2
C Interface
The I
2
C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries
the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit
serial and bi-directional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. The
figure below shows the data transfer format.
Figure 3 - Data Transfer Format for I
2
C Interface
2.5.1 Start Condition
Generated by the master, the MVTX2802AG. The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA
line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I
2
C bus
is free, both lines are High.
2.5.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.5.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.5.4 Acknowledgment
Like all clock pulses, the master generates the acknowledgment-related clock pulse. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down
the SDA line during acknowledge pulse so that it remains stable Low during the High period of this clock pulse.
An acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts
the transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line
to let the master generate the Stop condition.
START
SLAVE ADDRESS
R/W
ACK
DATA 1 (8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
相關PDF資料
PDF描述
MVTX2803 Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2803AG Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2804 8-Port 1000 Mbps Ethernet Distributed Switch
MVTX2804AG 8-Port 1000 Mbps Ethernet Distributed Switch
MVV200 Analog IC
相關代理商/技術參數(shù)
參數(shù)描述
MVTX2803 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2803A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 8 port Gigabit Ethernet switch
MVTX2803AG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 8-Port 1000 Mbps Ethernet Switch
MVTX2803AG2 制造商:Microsemi Corporation 功能描述:
MVTX2804 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port 1000 Mbps Ethernet Distributed Switch
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*