參數(shù)資料
型號: MVTX2802AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Managed 4-Port 1000 Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝: 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù): 76/154頁
文件大?。?/td> 1936K
代理商: MVTX2802AG
MVTX2802
Data Sheet
76
Zarlink Semiconductor Inc.
11.9.1.4 AVPML – VLAN Priority Map
I
2
C Address h041; CPU Address:h503
Accessed by CPU, serial interface and I
2
C (R/W)
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit
priorities. Under the internal transmit priority, “seven” is the highest priority where as “zero” is the lowest. This
feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7
into bit 2:0 of the AVPML register would map packet VLAN priority) into internal transmit priority 7. The new priority
is used only inside the 2802. When the packet goes out it carries the original priority.
11.9.1.5 AVPMM – VLAN Priority Map
I
2
C Address h042, CPU Address:h504
Accessed by CPU, serial interface and I
2
C (R/W)
Map VLAN priority into eight level transmit priorities:
11.9.1.6 AVPMH – VLAN Priority Map
I
2
C Address h043, CPU Address:h505
Accessed by CPU, serial interface and I
2
C (R/W)
7
6
5
3
2
0
VP2
VP1
VP0
Bit [2:0]:
Mapped priority of 0
(Default 000)
Bit [5:3]:
Mapped priority of 1
(Default 001)
Bit [7:6]:
Mapped priority of 2
(Default 10)
7
6
4
3
1
0
VP5
VP4
VP3
VP2
Bit [0]:
Mapped priority of 2
(Default 0)
Bit [3:1]:
Mapped priority of 3
(Default 011)
Bit [6:4]:
Mapped priority of 4
(Default 100)
Bit [7]:
Mapped priority of 5
(Default 1)
7
5
4
2
1
0
VP7
VP6
VP5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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