參數(shù)資料
型號： MVTX2803AG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Unmanaged 8-Port 1000 Mbps Ethernet Switch
中文描述： DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝： 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù)： 101/127頁
文件大?。?/td> 1706K
代理商： MVTX2803AG
MVTX2803
Data Sheet
101
Zarlink Semiconductor Inc.
V26, W29, W30, Y28, W26,
Y29, W27, Y30
AB26, AE27, AE28, AC27,
AE29, AC26, AE30, AD26
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
AG22, AG21, AG20, AF22,
AK21, AK20, AF21, AJ20
AG16, AF16, AG15, AF18,
AF15, AH15, AJ15, AG14
AG11, AJ10, AF11, AF10,
AG9, AF9, AH9, AJ9
AF6, AJ5, AF5, AG6, AK4,
AF4, AK3, AH4
AF1, AC5, AE1, AE2, AE3,
AC4, AE4, AD1
G7_RXD[7:0]
G6_RXD[7:0]
G5_RXD[7:0]
G4_RXD[7:0]
G3_RXD[7:0]
G2_RXD[7:0]
G1_RXD[7:0]
G0_RXD[7:0]
Input w/ pull up
G[7:0]port – PMA Receive Data Bit
[7:0]
W28, AD30, AK28, AH22,
AH16, AH10, AK5, AD5
G[7:0]_RX_D[8]
Input w/ pull down
G[7:0]port – PMA Receive Data Bit
[8]
V27, AD27, AJ28, AH23,
AF19, AG12, AK6, AF2
G[7:0]_RX_D[9]
Input w/ pull up
G[7:0]port – PMA Receive Data Bit
[9]
AA28, AF29, AJ26, AJ21,
AF14, AK10, AJ4, AD3
G[7:0]_RXCLK1
Input w/ pull up
G[7:0]port – PMA Receive Clock 1
AA29, AF27, AK26, AH21,
AH14, AG10, AH5, AC1
G[7:0]_RXCLK0
Input w/ pull up
G[7:0]port – PMA Receive Clock 0
AB28, Y26, AB29, AB30,
AA27, AC28, AC29, AA26
AE26, AF28, AG30, AG28,
AG27, AH29, AH28, AJ30
AK24, AJ24, AG24, AF24,
AH24, AF23, AK23, AJ23
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
AK14, AF13, AH13, AK13,
AH12, AJ12, AF12, AK12
AF8, AJ8, AK8, AG7, AG8,
AJ7, AK7, AF7
AG4, AK1, AJ1, AJ2, AH2,
AH1, AG1, AE5
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G7_TXD[7:0]
G6_TXD[7:0]
G5_TXD[7:0]
G4_TXD[7:0]
G3_TXD[7:0]
G2_TXD[7:0]
G1_TXD[7:0]
G0_TXD[7:0]
Output
G[7:0]port – PMA Transmit Data Bit
[7:0]
1Y27, AG29, AH25, AK19,
AG13, AH8, AK2, AD2
2G[7:0]_TXD[8]
3Output w/ pull up
4G[7:0]port – PMA Transmit Data
Bit [8]
AB27, AF30, AF25, AH20,
AJ14, AK9, AJ3, AB5
G[7:0]_TX_D[9]
Output w/ pull up
G[7:0]port – PMA Transmit Data Bit
[9]
AD28, AH30, AK22, AH17,
AH11, AG5, AG2, AB4
G[7:0]_ TXCLK
Output
G[7:0]port – PMA Gigabit Transmit
Clock
Ball No(s)
Symbol
I/O
Description
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