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參數(shù)資料
| 型號： | MVTX2803AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Unmanaged 8-Port 1000 Mbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA596 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596 |
| 文件頁數(shù)： | 23/127頁 |
| 文件大小： | 1706K |
| 代理商： | MVTX2803AG |
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MVTX2803
Data Sheet
23
Zarlink Semiconductor Inc.
7.7 WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behavior of the WRED logic.
In the table, |Px| is the byte count in queue Px. The WRED logic has three drop levels, depending on the value of N,
which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals 16|P7| +
16|P6| + 8|P5| + 4|P4| + 2|P3| + |P2|. If WFQ scheduling is used, N equals |P7| + |P6| + |P5| + |P4| + |P3| + |P2|.
Each drop level has defined high-drop and low-drop percentages, which indicate the percentage of high-drop and
low-drop packets that will be dropped at that level. The X, Y, and Z percent parameters can be programmed using
the registers RDRC0 and RDRC1. Parameters A-F are the byte count thresholds for each priority queue, and are
also programmable. When using delay bound scheduling, the values selected for A-F also control the approximate
bandwidth partition among the traffic classes; see application note.
7.8 Buffer Management
Because the number of frame data buffer (FDB) slots is a scarce resource, and because it is desirable to ensure
that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class,
the concept of buffer management was produced into the MVTX2803AG. The buffer management scheme is
designed to divide the total buffer space into numerous reserved regions and one shared pool, (see Figure 4).
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames
stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the
frame first enters the MVTX2803AG, its destination port and class are as yet unknown, and so the decision to
drop or not needs to be temporarily postponed. This ensures that every frame can be received first before
subjecting it to the frame drop discipline after classifying.
Six reserved sections, one for each of the highest six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation.
Another segment of the FDB reserves space for each of the 8 ports. These source port buffer reservations are
programmable. These 8 reserved regions make sure that no well-behaved source port can be blocked by
another misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The registers related to the Buffer
Management logic are:
PRG- Port Reservation for Gigabit Ports
SFCB- Share FCB Size
C2RS- Class 2 Reserved Size
C3RS- Class 3 Reserved Size
C4RS- Class 4 Reserved Size
C5RS- Class 5 Reserved Size
C6RS- Class 6 Reserved Size
C7RS- Class 7 Reserved Size
P7
P6
P5
P4
P3
P2
High Drop
Low Drop
Level 1
N
≥
240
|P7|
≥
A
KB
|P6|
≥
B
KB
|P5|
≥
C
KB
|P4|
≥
D
KB
|P3|
≥
E
KB
|P2|
≥
F
KB
X%
0%
Level 2
N
≥
280
Y%
Z%
Level 3
N
≥
320
100%
100%
Table 3 - WRED Dropping Scheme
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2803AG2 | 制造商:Microsemi Corporation 功能描述: |
| MVTX2804 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port 1000 Mbps Ethernet Distributed Switch |
| MVTX2804AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port 1000 Mbps Ethernet Distributed Switch |
| MVTX2804AG2 | 制造商:Microsemi Corporation 功能描述: |
| MVU10-10FBK | 功能描述:端子 D-10-1103K BS-33-10-P 85299 RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點(diǎn)電鍍:Tin over Nickel 觸點(diǎn)材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
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