參數(shù)資料
型號(hào): MVTX2804
廠商: Zarlink Semiconductor Inc.
英文描述: 8-Port 1000 Mbps Ethernet Distributed Switch
中文描述: 8端口1000 Mbps以太網(wǎng)交換機(jī)分布式
文件頁(yè)數(shù): 20/174頁(yè)
文件大?。?/td> 2249K
代理商: MVTX2804
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MVTX2804
Data Sheet
20
Zarlink Semiconductor Inc.
Note:
Deleting IP Multicast address requests by the MVTX2804 occur when the CPU issues a Learn IP Multicast
address command but the search engine discovers no RAM space for storage.
The format of the Control Frame is described in the processor interface application note.
2.4 Unmanaged Mode
In unmanaged mode, the MVTX2804 can be configured by EEPROM (24C02 or compatible) via an I
2
C interface
at boot time, or via a synchronous serial interface during operation. When the bootstrap Td[8] is set to ‘0’
meaning EEPROM installed, the MVTX2804, acting as a master starts the data transfer from the memory to the
switch.
2.5 I
2
C Interface
The I
2
C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries
the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit
serial and bi-directional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. The
figure below shows the data transfer format.
Figure 3 - Data Transfer Format for I
2
C Interface
2.5.1 Start Condition
Generated by the master, the MVTX2804. The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA
line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I
2
C bus
is free, both lines are High.
2.5.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.5.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.5.4 Acknowledgment
Like all clock pulses, the master generates the acknowledgment-related clock pulse. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down
the SDA line during acknowledge pulse so that it remains stable Low during the High period of this clock pulse.
An acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts
the transfer.
START
SLAVE
ADDRESS
R/W
ACK
DATA 1
(8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MVTX2804AG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:8-Port 1000 Mbps Ethernet Distributed Switch
MVTX2804AG2 制造商:Microsemi Corporation 功能描述:
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MVU10-10FBX 功能描述:端子 BLOCK FORK VNYL INS BTL BS-33-10-P RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點(diǎn)電鍍:Tin over Nickel 觸點(diǎn)材料:Beryllium Copper, Phosphor Bronze 端接類(lèi)型:Crimp
MVU10-10FBX-BOTTLE 功能描述:CONN FORK BLOCK INSUL 50PC RoHS:是 類(lèi)別:連接器,互連式 >> 端子 - 鏟形 系列:Scotchlok™ 標(biāo)準(zhǔn)包裝:1 系列:Scotchlok™ 端子類(lèi)型:彈簧,壓接式 接線柱/接片尺寸:10 接線柱 寬度 - 外邊:0.320"(8.13mm) 長(zhǎng)度 - 總體:1.030"(26.16mm) 安裝類(lèi)型:自由懸掛 端子:壓接 線規(guī):10-12 AWG 絕緣體:絕緣 特點(diǎn):- 顏色:黃 包裝:散裝 觸點(diǎn)表面涂層:錫 觸點(diǎn)材料:銅,ETP 絕緣體直徑:0.250"(6.35mm) 材料 - 絕緣體:聚酰胺(PA),尼龍 長(zhǎng)度 - 環(huán)心道末端:0.280"(7.11mm) 長(zhǎng)度 - 末端:0.550"(13.97mm) 內(nèi)部舌簧打開(kāi):- 相關(guān)產(chǎn)品:TR-490-ND - HAND CRIMP TOOL RACHET 10-22 AWGTH-450-ND - TOOL HAND CRIMP 6-26AWGTR-482-ND - TOOL RATCHETING 10-22AWG CRIMP920099-R-ND - TOOL 10-22AWG SCOTCHLOK CRIMP 其它名稱(chēng):000511285879115112858791180611464373