
MX98216EC
P/N:PM0781
REV. 0.2, Apr, 18, 2001
21
29.5-3
PHY/ALR Command
In PHY register access
000 : A searching function for PHY ID and PHY register number when
CPU access data filled relevant information.
001 : A command for switch internal control register to CPU access data
based on read operation or a command for CPU access data to
register to switch internal control register based on write operation.
100 : A command for content of PHY register to switch internal control
register based on read operation or a command for switch internal
control register to PHY register based on write operation.
In address table access
000 : MAC ID for address bit [15:0] access from CPU access data to
switch internal control register based on CPU write operation.
It
also can be MAC ID access bit [15:0] from switch internal control
register to CPU access data based on CPU read operation.
001 : MAC ID for address bit [31:16] access from CPU access data to
internal control register and based on CPU write operation; and vice
versa.
010 : MAC ID for address bit [47:32] access from CPU access data to
switch internal control register based on CPU write operation; and
vice versa.
011 : Status of address table entry access like port number bit [8:4], aging
timer bit [3:1], and valid bit [0] from switch internal control register to
CPU access data based on CPU read operation.
100 : Based on read operation from content of an address table entry to
switch internal control register or write operation from switch internal
control register to content of an address table entry.
R/W
0x0H
29.10-6
Frozen Port
The switch provides frozen function for an entry in address table; that is,
an entry with learned MAC address and port number as an input will
protect not to be aging out when the port number and assigned MAC have
been set. Frozen function can only work on the first layer of address
table.
It’ s because the entry of second-layer of address table should be
for dynamic MAC address.
If frozen port sets to all one and CPU
read/write command is one, the frozen MAC address will be released.
If
frozen port sets all one and CPU read/write command is zero, the host
processor will read the content of second layer of address table.
R/W
0x00H
29.15-11
Reserved
R/W
0x00H
Flow Control Enable (8-15) (Reg2AH), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
2A.7-0
Flow Control Enable
IEEE 802.3x flow control for port 8-15.
One bit per port; e.g. bit 0 for port
8 and bit 7 for port 15.
0 : disable
1 : enable
R/W
0x00H
2A.15-8
N/A