參數(shù)資料
型號(hào)： MX98715AL
英文描述： SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)卡控制器
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 215K
代理商： MX98715AL
17
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
TABLE 5.2.1 FATAL BUS ERROR BITS
CSR5<25:23>
000
001
010
011
1XX
Process State
parity error for either SERR# or PERR#, cleared by software reset.
master abort
target abort
reserved
reserved
TABLE 5.2.2 TRANSMIT PROCESS STATE
CSR5<22:20>
000
001
010
011
100
101
110
111
Process State
Stopped- reset or transmit jabber expired.
Fetching transmit descriptor
Waiting for end of transmission
filling transmit FIFO
reserved
Setup packet
Suspended, either FIFO underflow or unavailable transmit descriptor
closing transmit descriptor
TABLE 5.2.3 RECEIVE PROCESS STATE
CSR5<19:17>
000
010
011
100
101
110
111
Process State
Stopped- reset or stop receive command. Fetching receive descriptor
checking for end of receive packet
Waiting for receive packet
Suspended, receive buffer unavailable
closing receive descriptor
Purging the current frame from the receive FIFO due to unavailable receive buffer
queuing the receive frame from the receive FIFO into host receive buffer
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