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參數(shù)資料
| 型號： | MX98905BFC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng)， |
| 文件頁數(shù)： | 61/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905BFC |
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61
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
14. RECEIVE STATUS REGISTER (RSR) 0CH (READ)
This register records status of the received packet. It
includes information on errors, the type of address
match, either physical or multicast, and the aborted
packet type. The contents of this register are written to
buffer memory by the DMA after receiving a good
packet. If packets with errors are to be saved the
receive status is written to memory at the head of the
erroneous packet, when an erroneous packet is
received. If packets with errors are to be rejected the
RSR will not be written to memory. The contents will be
cleared when the next packet arrives. CRC errors,
frame alignment errors and missed packets are
counted internally by the ENC, which relinquishes the
host from reading the RSR in real time to record errors
for Network Management Functions. The contents of
this register are not specified until after the first
reception.
PRX
CRC
FAE
FO
MPA
PHY
DIS
DFR
0
1
2
3
4
5
6
7
Bits
SYMBOL
BIT
DESCRIPTION
PRX
D0
PACKET RECEIVED CORRECTLY
: Indicates packet received without error. (Bits
CRC, FAE, FO and MPA are zero for the received packet.) Set when packets are
received complete.
CRC
D1
CRC ERROR
: Indicates packet received with CRC error. Increments Tally Counter
(CNTR1). This bit will also be set for Frame Alignment errors. Set when packets are
received complete.
FAE
D2
FRAME ALIGNMENT ERROR
: Indicates that the incoming packet did not end on a
byte boundary and the CRC did not match at last byte boundary. Increments Tally
Counter (CNTR0). Set when packets are received complete.
FO
D3
FIFO OVERRUN:
This bit is set when the FIFO is not serviced causing overflow
during reception. Reception of the packet will be aborted.
MPA
D4
MISSED PACKET
: Set when packet intended for node cannot be accepted by ENC
because of a lack of receive buffers, or if the controller is in monitor mode and did not
buffer the packet to memory increments Tally Counter (CNTR2).
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