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參數(shù)資料
| 型號： | MX98905BFC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng)， |
| 文件頁數(shù)： | 81/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905BFC |
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81
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
AC CHARACTRISTICS
(Continued)
SYMBOL
PARAMETER
8 BIT
16 BIT
UNIT
MIN.
MAX.
MIN.
MAX.
T33
MSWR1deasserted to MSMD0-15
20
20
ns
invalid (Note 3)
T34
MEMA1-15 valid before /MSWRL
20
20
ns
asserted
T35
RCSXL or /BPCSL asserted to CHRDY
15
15
ns
asserted (Note 11)
T36
MSRDL, MSWRL asserted to CHRDY
0
0
ns
asserted
T37
MEMA1-15 valid to CHRDY asserted
15
15
ns
T38a
Driving data from SD0-15 on to
60
60
ns
MEMD0-15 to CHRDY asserted for
RAM access
T38b
Driving data from SD0-15 to CHRDY
260
260
ns
asserted for Boot PROM access
Note 1:
M16L, IO16 are only asserted for 16-bit transfers.
Note 2:
CHRDY is only deasserted if the NIC core cannot service the access immediately. It is held deasserted until the NIC core is ready,
causing the system to insert wait states.
Note 3:
On 8-bit trnasfers only 8 bits of MEHD0-15 and D0-7 are driven.
Note 4:
This is the earty CHRDY timing required by some machines, where CHRDY is referenced to BALE. In this mode of operation, under
certain circumstances, CHRDY will be asserted for cycles which are not for this device i.e., memory cycles or I/O cycles where SA0-9
match our address before reaching their valid state. In such a case the time to assert CHRDY, from MRDL, MWRL or SA0-9 invalid,
will be the same as the deassertion time specified.
Note 5:
This is the standard CHRDY timing where CHRDY is asserted after IORDL or IOWRL.
Note 6
: Read data valid is referenced to CHRDY when wait states have been inserted.
Note 7:
If no wait states are inserted read data valid can be measured from IORDL.
Note 8:
This is a minimum timing with no additional wait states.
Note 9:
This is the standard I/O 16 timing where /IO16 is asserted after a valid address decode and IORDL or IOWRL going active.
Note 10:
This is the late IO16L timing, required by some machines. Where IO16L is asserted after a valid address decode and IORDL or
IOWRL going active.
Note 11:
BPCS is asserted for a boot PROM access. RCSL for a RAM access. RCSXL refers to RCS1L and RCS2L Depending on the mode
of operation either or both can be asserted. See the Functional Bus Timing section for further explanation.
Note 12:
Specifications which measure delays from an active state to a high impedance state are not guaranteed by production test, but are
characterized and correlated to determine true driver turn-off time by simulating inherent R-C delay times. In test measurements.
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