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參數(shù)資料
| 型號(hào)： | N02L163WN1AB2-55I |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, GREEN, BGA-48 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大小： | 184K |
| 代理商： | N02L163WN1AB2-55I |
(DOC# 14-02-014 REV N ECN# 01-1267)
6
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.
N02L163WN1A
AMI Semiconductor, Inc.
Timing Test Conditions
Item
Input Pulse Level
0.1VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 VCC
Output Load
CL = 30pF
Operating Temperature
-40 to +85 oC
Timing
Item
Symbol
2.3 - 3.6 V
2.7 - 3.6 V
Units
Min.
Max.
Min.
Max.
Read Cycle Time
tRC
70
55
ns
Address Access Time
tAA
70
55
ns
Chip Enable to Valid Output
tCO
70
55
ns
Output Enable to Valid Output
tOE
35
30
ns
Byte Select to Valid Output
tLB, tUB
35
30
ns
Chip Enable to Low-Z output
tLZ
10
ns
Output Enable to Low-Z Output
tOLZ
55
ns
Byte Select to Low-Z Output
tLBZ, tUBZ
10
ns
Chip Disable to High-Z Output
tHZ
0200
20
ns
Output Disable to High-Z Output
tOHZ
0200
20
ns
Byte Select Disable to High-Z Output
tLBHZ, tUBHZ
0200
20
ns
Output Hold from Address Change
tOH
10
ns
Write Cycle Time
tWC
70
55
ns
Chip Enable to End of Write
tCW
50
40
ns
Address Valid to End of Write
tAW
50
40
ns
Byte Select to End of Write
tLBW, tUBW
50
40
ns
Write Pulse Width
tWP
40
ns
Address Setup Time
tAS
00
ns
Write Recovery Time
tWR
00
ns
Write to High-Z Output
tWHZ
20
ns
Data to Write Time Overlap
tDW
40
35
ns
Data Hold from Write Time
tDH
00
ns
End Write to Low-Z Output
tOW
10
ns
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| N02L163WN1AB-55I | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:2Mb Ultra-Low Power Asynchronous CMOS SRAM |
| N02L163WN1AT | 制造商:NANOAMP 制造商全稱:NANOAMP 功能描述:2Mb Ultra-Low Power Asynchronous CMOS SRAM |
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| N02L163WN1AT2-55I | 制造商:ON Semiconductor 功能描述:N02L163WN1A Series 2 Mbit ( 128 K X 16 ) Asynchronous CMOS SRAM - TSOP II-44 |
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