SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES" />
參數(shù)資料
型號: NCN8025AMNGEVB
廠商: ON Semiconductor
文件頁數(shù): 14/15頁
文件大?。?/td> 0K
描述: BOARD EVAL SMART CARD INTERFACE
設(shè)計資源: NCN8025AMNGEVB Test Procedure
NCN8025AMNGEVB Gerber Zip
NCN8025AMNGEVB Bill of Materials
NCN8025AMNGEVB Schematic
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,智能卡
嵌入式:
已用 IC / 零件: NCN8025A
已供物品:
其它名稱: NCN8025AMNGEVB-ND
NCN8025AMNGEVBOS
NCN8025 / NCN8025A
http://onsemi.com
8
SMART CARD INTERFACE SECTION CI/O, CAUX1, CAUX2, CCLK, CRST, PRES, PRES (VDD = 3.3 V; VDDP = 5 V; Tamb = 25°C;
FCLKIN = 10 MHz)
Symbol
Rating
Min
Typ
Max
Unit
VOH
VOL
tR
tF
tR/F
td
CRST @ CVCC = 1.8 V, 3.0 V, 5.0 V
Output RESET VOH @ Irst = 200 mA
Output RESET VOL @ Irst = 200 mA
Output RESET Rise time @ Cout = 100 pF (Note 9)
Output RESET Fall time @ Cout = 100 pF (Note 9)
Output Rise/Fall times @ CVCC = 1.8 V & Cout = 100 pF (Note 9)
RSTIN to CRST delay Reset enabled (Note 9)
0.9 x CVCC
0
CVCC
0.20
100
200
2
V
ns
ms
FCRDCLK
VOH
VOL
FDC
trills
tulsa
SR
CCLK @ CVCC = 1.8 V, 3.0 V or 5.0 V
Output Frequency (Note 9)
Output CCLK VOH @ Iclk = 200 mA
Output CCLK VOL @ Iclk = 200 mA
Output Duty Cycle (Note 9)
Rise & Fall time
Output CCLK Rise time @ Cout = 33 pF (Note 9)
Output CCLK Fall time @ Cout = 33 pF (Note 9)
Slew Rate @ Cout = 33 pF (CVCC = 3.0 V or 5.0 V) (Note 9)
0.9 x CVCC
0
45
0.2
27
CVCC
+0.2
55
16
MHz
V
%
ns
V/ns
VIH
VIL
|IIL|
|IIH|
VOH
VOL
tRi / Fi
tRo / Fo
CAUX1, CAUX2, CI/O @ CVCC = 1.8 V, 3.0 V, 5.0 V
Input Voltage High Level
1.8 V Mode
3.0 V Mode
5.0 V Mode
Input Voltage Low Level
1.8 V mode
3.0 V and 5.0 V modes
Low Level Input current VIL = 0 V
High Level Input current VIH = CVCC
Output VOH
@ IOH = 40 mA for CVCC = 3.0 V and 5.0 V
@ IOH = 20 mA for CVCC = 1.8 V
Output VOL
@ IOL = 1 mA, VIL = 0 V
Input Rising/Falling times (Note 9)
Output Rising/Falling times / Cout = 80 pF (Note 9)
1.2
1.6
2.3
0.30
0.75 x CVCC
0
CVCC + 0.3
0.50
0.80
600
10
CVCC + 0.1
0.30
1.2
0.1
V
mA
V
ms
Fbidi
Maximum data rate through bidirectional I/O, AUX1 & AUX2 channels (Note 9)
1
MHz
RPU
CAUX1, CAUX2, CI/O Pull Up Resistor
8
11
16
kW
tIO
Propagation delay IOuc > CI/O and CI/O > IOuc (falling edge) (Note 9)
200
ns
tpu
Active pullup pulse width buffers I/O, AUX1 and AUX2 (Note 9)
200
ns
Cin
Input Capacitance on data channels
10
pF
VIH
VIL
PRES, PRES
Card Presence Voltage High Level
Card Presence Voltage Low Level
0.7 x VDD
0.3
VDD + 0.3
0.3 x VDD
V
|IIH|
|IIL|
PRES, PRES
High level input leakage current, VIH = VDD
PRES
Low level input leakage current, VIL = 0 V
PRES
5
10
1
10
mA
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