- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361101 > NCP500 (ON SEMICONDUCTOR) 150 mA CMOS Low Noise Low-Dropout Voltage Regulator(150 mA， CMOS，低噪聲，低壓差穩(wěn)壓器) PDF資料下載
參數(shù)資料
| 型號(hào)： | NCP500 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 150 mA CMOS Low Noise Low-Dropout Voltage Regulator(150 mA， CMOS，低噪聲，低壓差穩(wěn)壓器) |
| 中文描述： | 一五〇毫安CMOS低噪聲低壓差穩(wěn)壓器（150毫安的CMOS，低噪聲，低壓差穩(wěn)壓器） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 142K |
| 代理商： | NCP500 |
NCP500
http://onsemi.com
14
APPLICATIONS INFORMATION
The NCP500 series regulators are protected with internal
thermal shutdown and internal current limit. A typical
application circuit is shown in Figure 27.
Input Decoupling (C1)
A 1.0
recommended and should be connected close to the NCP500
package. Higher values and lower ESR will improve the
overall line transient response.
F capacitor either ceramic or tantalum is
Output Decoupling (C2)
The NCP500 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) or a
minimum output current. The minimum decoupling value is
1.0 F and can be augmented to fulfill stringent load
transient requirements. The regulator accepts ceramic chip
capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response. Figure 29 shows the stability region for a range of
operating conditions and ESR values.
Noise Decoupling
The NCP500 is a low noise regulator without the need of
an external bypass capacitor. It typically reaches a noise level
of 50 VRMS overall noise between 10 Hz and 100 kHz. The
classical bypass capacitor impacts the start up phase of
standard LDOs. However, thanks to its low noise
architecture, the NCP500 operates without a bypass element
and thus offers a typical 20 s start up phase.
Enable Operation
The enable pin will turn on or off the regulator. These
limits of threshold are covered in the electrical specification
section of this data sheet. The turnon/turnoff transient
voltage being supplied to the enable pin should exceed a
slew rate of 10 mV/ s to ensure correct operation. If the
enable is not to be used then the pin should be connected
to V
in
.
Thermal
As power across the NCP500 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
effect the rate of junction temperature rise for the part. This
is stating that when the NCP500 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
The maximum dissipation the package can handle is
given by:
TJ(max)
PD
TA
RJA
If T
J
is not recommended to exceed 125
°
C, then the
NCP500 can dissipate up to 400 mW @ 25
°
C.
The power dissipated by the NCP500 can be calculated
from the following equation:
Ptot
[Vin* Ignd(Iout)]
or
[Vin
Vout] * Iout
VinMAX
Ptot
Vout*Iout
Ignd
Iout
If a 150 mA output current is needed the ground current
is extracted from the data sheet curves: 200 A @ 150 mA.
For a NCP500SN18T1 (1.8 V), the maximum input voltage
will then be 4.4 V, good for a 1 Cell Liion battery.
Hints
Please be sure the V
in
and GND lines are sufficiently wide.
When the impedance of these lines is high, there is a chance
to pick up noise or cause the regulator to malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short
as possible.
Package Placement
DFN packages can be placed using standard pick and
place equipment with an accuracy of
Component pick and place systems are composed of a vision
system that recognizes and positions the component and a
mechanical system which physically performs the pick and
place operation. Two commonly used types of vision
systems are: (1) a vision system that locates a package
silhouette and (2) a vision system that locates individual
bumps on the interconnect pattern. The latter type renders
more accurate place but tends to be more expensive and time
consuming. Both methods are acceptable since the parts
align due to a selfcentering feature of the DFN solder joint
during solder reflow.
0.05 mm.
Solder Paste
Type 3 or Type 4 solder paste is acceptable.
Reflow and Cleaning
The DFN may be assembled using standard IR/IR
convection SMT reflow processes without any special
considerations. As with other packages, the thermal profile
for specific board locations must be determined. Nitrogen
purge is recommended during solder for noclean fluxes.
The DFN is qualified for up to three reflow cycles at 235
°
C
peak (JSTD020). The actual temperature of the DFN is a
function of:
Component density
Component location on the board
Size of surrounding components
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NCP502SN28T1G | 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator |
| NCP502SN29T1G | 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator |
| NCP502SN31T1G | 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator |
| NCP502SN33T1G | 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator |
| NCP502SN34T1G | 80 mA CMOS Low Iq, Low−Dropout Voltage Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCP500/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:150 mA CMOS Low Noise Low-Dropout Voltage Regulator |
| NCP500_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:150 mA CMOS Low Noise Low−Dropout Voltage Regulator |
| NCP5005 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Compact Backlight LED Boost Driver |
| NCP5005GEVB | 功能描述:電源管理IC開發(fā)工具 NCP5005 EVAL BRD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| NCP5005SNT1G | 功能描述:LED照明驅(qū)動(dòng)器 ANA WHITE LED DRIVER RoHS:否 制造商:STMicroelectronics 輸入電壓:11.5 V to 23 V 工作頻率: 最大電源電流:1.7 mA 輸出電流: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SO-16N |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。