參數(shù)資料
型號(hào)： OQ2541BHP
英文描述： CLOCK/DATA RECOVERY|BIPOLAR|QFP|48PIN|PLASTIC
中文描述： 時(shí)鐘/數(shù)據(jù)恢復(fù)|雙極| QFP封裝| 48PIN |塑料
文件頁(yè)數(shù)： 6/40頁(yè)
文件大?。?/td> 292K
代理商： OQ2541BHP
2000 Sep 18
6
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
FUNCTIONAL DESCRIPTION
The OQ2541B recovers data and clock signals from an
incoming high speed bitstream. The input signal on
pins DIN and DINQ is buffered and amplified by the input
circuit (see Fig.1). The signal is then fed into the Alexander
phase detector, where the phase of the incoming data
signal is compared with that of the internal clock. If the
signals are out of phase, the phase detector generates
correction pulses (up or down) that shift the phase of the
Voltage Controlled Ring Oscillator (VCRO) output in
discrete amounts (
) until the clock and data signals are
in phase. The technique used is based on principles first
proposed by J.D.H. Alexander, hence the name of the
phase detector.
Data sampling
The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked):
A is the centre of the data bit
T is in the vicinity of the next transition
B is in the centre of the bit following the transition.
If the same level is recorded at both A and B, a transition
has not occurred and no action is taken, regardless of
level T. However, if levels A and B are different, a
transition has occurred and the phase detector uses
level T to determine whether the clock was too early or too
late with respect to the data transition.
If levels A and T are the same but different from level B,
the clock was too early and needs to be slowed down a
little. The Alexander phase detector then generates a
down pulse which stretches a single output pulse from the
ring oscillator by approximately 0.25% which is 1 ps of the
400 ps bit period in the STM16/OC48 mode. This forces
the VCRO to run at a slightly lower frequency for one bit
period. The phase of the clock signal is thus shifted
fractionally with respect to the data signal.
If, on the other hand, levels B and T are the same but
different from level A, the clock was too late and needs to
be speeded up for synchronization. The phase detector
generates an up pulse, forcing the VCRO to run at a
slightly higher frequency (+0.25%) for one bit period. The
phase of the clock signal is shifted with respect to the data
signal (as above, but in the opposite direction). While
making these phase adjustments, only the proportional
path is active. Because the instantaneous frequency of the
VCRO can be changed in one of two discrete steps only
(
±
0.25%), this type of loop is also known as a Bang/Bang
Phase-Locked Loop (PLL).
If not only the phase but also the frequency of the VCRO
is incorrect, a long train of up or down pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, only the phase needs to be adjusted for
synchronization. The proportional path adjusts the phase
of the clock signal, whereas the integrating path adjusts
the centre frequency.
Frequency window detector
The frequency window detector checks the VCRO
frequency, which has to be within a 1000 ppm (parts per
million) window around the required frequency.
The detector compares the output of frequency divider 2
with the reference frequency on pins CREF and CREFQ
(19.44 or 38.88 MHz;see Table 2).IftheVCROfrequency
is found to be outside this window, the frequency window
detector disables the Alexander phase detector and forces
the VCRO output to a frequency within the window. Then,
the phase detector starts acquiring lock again. Due to the
loosecouplingof1000 ppm,thereferencefrequencydoes
notneedtobehighlyaccurateorstable.Any crystal-based
oscillator that generates a reasonably accurate frequency
(e.g. 100 ppm) will do.
Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers that are capable of driving a 50
load.
RF data and clock input circuit
The schematic of the input circuit is shown in Fig.4.
RF data and clock output circuit
The schematic of the output circuit is shown in Fig.5.
handbook, halfpage
MGK143
CLOCK
A
T
B
Fig.3 Data sampling.
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