參數(shù)資料
型號： ORT4622
英文描述： Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù)： 2/90頁
文件大?。?/td> 1915K
代理商： ORT4622
Table of Contents
Contents
Introduction ............................................................... 1
Embedded Core Features ......................................... 1
FPSC Highlights ........................................................ 4
Software Support ...................................................... 4
Description ................................................................ 5
What Is an FPSC .................................................. 5
FPSC Overview ...................................................... 5
FPSC Gate Counting .............................................. 5
FPGA/Embedded Core Interface ............................ 5
ORCA Foundry Development System .................... 5
FPSC Design Kit ..................................................... 6
FPGA Logic Overview ............................................ 6
PLC Logic ............................................................... 6
PIC Logic ................................................................ 7
System Features .................................................... 7
Routing ................................................................... 7
Configuration .......................................................... 7
More Series 3 Information ...................................... 7
ORT4622 Overview ................................................... 8
Device Layout ......................................................... 8
Backplane Transceiver Interface ............................ 8
HSI Interface ........................................................... 10
STM Macrocell ........................................................ 10
CPU Interface ......................................................... 10
FPGA Interface ....................................................... 10
FPSC Configuration ................................................ 12
Generic Backplane Transceiver Application .............. 13
Backplane Transceiver Core Detailed Description .... 13
HSI Macro ............................................................... 13
STM Transmitter (FPGA -> Backplane) .................. 15
STM Receiver (Backplane -> FPGA) ...................... 19
Powerdown Mode ................................................... 25
Redundancy and Protection Switching ................... 25
Memory Map ............................................................. 26
Definition of Register Types ................................... 26
Memory Map Overview ........................................... 27
Powerup Sequencing for ORT4622 Device .............. 35
FPGA Configuration Data Format ............................. 36
Using ORCAFoundry to Generate Configuration
RAM Data ............................................................ 36
FPGA Configuration Data Frame ........................... 36
Bit Stream Error Checking ......................................... 38
FPGA Configuration Modes ...................................... 38
Absolute Maximum Ratings ....................................... 39
Recommend Operating Conditions ........................... 39
Electrical Characteristics ........................................... 40
HSI Circuit Specifications .......................................... 41
Input Data ............................................................... 41
Jitter Tolerance ....................................................... 41
Generated Output Jitter .......................................... 41
PLL ......................................................................... 41
Input Reference Clock ............................................ 41
HSI Circuit Specifications .......................................... 41
Page
Contents
Power Supply Decoupling LC Circuit ......................42
LVDS I/O ...................................................................43
LVDS Receiver Buffer Requirements .....................44
Timing Characteristics ...............................................45
Description ..............................................................45
PFU Timing .............................................................46
PLC Timing .............................................................46
SLIC Timing ............................................................46
PIO Timing ..............................................................46
Special Function Timing .........................................46
Clock Timing ...........................................................46
Configuration Timing ...............................................46
Readback Timing ....................................................46
Input/Output Buffer Measurement Conditions
(on-LVDS Buffer) ......................................................56
FPGA Output Buffer Characteristics .........................57
LVDS Buffer Characteristics ......................................58
Termination Resistor ...............................................58
LVDS Driver Buffer Capabilities ..............................58
Estimating Power Dissipation ....................................59
ORT4622 Clock Power ...........................................59
Pin Information ..........................................................60
Package Thermal Characteristics Summary .............83
Θ
JA .........................................................................83
ψ
JC .........................................................................83
Θ
JC .........................................................................83
Θ
JB .........................................................................83
FPGA Maximum Junction Temperature .................83
Package Thermal Characteristics .............................84
Package Coplanarity .................................................84
Package Parasitics ....................................................84
Package Outline Diagrams ........................................86
Terms and Definitions .............................................86
432-Pin EBGA ........................................................87
680-Pin PBGAM .....................................................88
Ordering Information .................................................90
Page
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Lucent Technologies
2
List of Figures
Figure 1. ORCA ORT4622 Block Diagram.................8
Figure 2. Architecture of ORT4622 Backplane
Transceiver..............................................................11
Figure 3. HSI Functional Block Diagram ....................14
Figure 4. Byte Ordering of Input/Output Interface in
STS-12 Mode...........................................................15
Figure 5. Interconnect of Streams for FIFO................20
Figure 6. Alignment of Four STS-12 Streams ............20
Figure 7. Examples of Link Alignment........................21
Figure 8. Pointer Mover State Machine......................22
Figure 9. SPE and C1J1 Functionality .......................24
Figure 10. SPE Stuff Bytes.........................................25
Figure 11. Serial Configuration Data Format—
Autoincrement Mode................................................37
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