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參數(shù)資料
| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 20/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORT4622 |
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20
Lucent Technologies Inc.
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
Backplane Transceiver Core Detailed
Description
(continued)
5-8577 (F)
Figure 5. Interconnect of Streams for FIFO
Alignment
The incoming data from the clock and data recovery
can be separated into four STS-12 channels (A, B, C,
and D). These streams can be frame aligned in the pat-
terns shown in Figure 6.
5-8575 (F)
Figure 6. Alignment of Four STS-12 Streams
There is also a provision to allow certain streams to be
disabled (i.e., not producing interrupts or affecting syn-
chronization). These streams can be enabled at a later
time without disrupting other streams.
The FIFO block consists of a 24 by 10-bit FIFO per link.
This FIFO is used to align up to ±154.3 ns of interlink
skew and to transfer to the system clock. The FIFO
sync circuit takes metastable hardened frame pulses
from the write control blocks and produces sync signals
that indicate when the read control blocks should begin
reading from the first FIFO location. On top of the sync
signals, this block produces an error indicator which
indicates that the signals to be aligned are too far apart
for alignment (i.e., greater than 18 clocks apart). Sync
and error signals are sent to read control block for
alignment. The read control block is synched only once
on start-up; any further synchronization is software
controlled. The action of resynching a read control
block will always cause loss of data. A register allows
the read control block to be resynched.
Link Alignment.
The general operation of the link
alignment algorithm is to wait 12 clocks (i.e., half the
FIFO) from the arriving frame pulse and then signal the
read control block to begin reading. For perfectly
aligned frame pulses across the links, it is simply a
matter of counting down 12 and then signaling the read
control block.
The algorithm down counts by one until all of the frame
pulses have arrived and then by two when they are all
present. For example (Figure 7), if all pulses arrive
together, then alignment algorithm would count 24
(12 clocks); if, however, the arriving pulses are spread
out over four clocks, then it would count one for the first
four pulses and then two per clock afterward, which
gives a total of 14 clocks between first frame pulse and
the first read. This puts the center of arriving frame
pulses at the halfway point in the buffer. This is the
extent of the algorithm, and it has no facility for actively
correcting problems once they occur.
The write control block receives byte-wide data at
77.76 MHz and a frame pulse two clocks before the
first A1 byte of the STS-12 frame. It generates the write
address for the FIFO block. The first A1 in every STS-
12 stream is written in the same location (address 0) in
the FIFO. Also, a frame bit is passed through the FIFO
along with the first byte before the first A1 of the STS-
12. The read control block synchronizes the reading of
the FIFO for streams that are to be aligned. Reading
begins when the FIFO sync signals that all of the appli-
cable A1s and the appropriate margin have been writ-
ten to the FIFO. All of the read blocks to be
synchronized begin reading at the same time and
same location in memory (address 0).
The alignment algorithm takes the difference between
read address and write address to indicate the relative
clock alignments between STS-12 streams. If this
depth indication exceeds certain limits (12 clocks), then
an interrupt is given to the microprocessor (alignment
overflow). Each STS-12 stream can be realigned by
software if it gets too far out of line (this would cause a
loss of data). For background applications that have
less than 154.3 ns of interlink skew, misalignment will
not occur.
STS-12
STREAM A
STS-12
STREAM B
STS-12
STREAM C
STS-12
STREAM D
FIFO
SYNC
STREAM A
STREAM B
STREAM C
STREAM D
STREAM A
STREAM B
STREAM C
STREAM D
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