參數(shù)資料
型號： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 4/112頁
文件大小： 2417K
代理商： ORT8850
4
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Embedded Core Features (Serial)
I
Implemented in an
ORCA
Series 4 FPGA.
I
Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
I
No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz
—
106 MHz
clock, and a frame pulse.
I
High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without exter-
nal clocks.
I
Eight-channel HSI function provides 850 Mbits/s
serial interface per channel for a total chip bandwidth
of 6.8 Gbits/s (full duplex).
I
HSI function uses Agere
’
s 850 Mbits/s serial inter-
face core. Rates from 212 Mbits/s to 850 Mbits/s are
supported directly (lower rates directly supported
through decimation and interpolation).
I
LVDS I/Os compliant with
EIA
-644 support hot
insertion. All embedded LVDS I/Os include both input
and output on-board termination to allow long-haul
driving of backplanes.
I
Low-power 1.5 V HSI core.
I
Low-power LVDS buffers.
I
Programmable STS-1, STS-3, and STS-12 framing.
I
Independent STS-1, STS-3, and STS-12 data
streams per quad channels.
I
8:1 data multiplexing/demultiplexing for 106.25 MHz
byte-wide data processing in FPGA logic.
I
On-chip, phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T recommendation
G.958.
I
Powerdown option of HSI receiver on a per-channel
basis.
I
Selectable 8B/10B coder/decoder or SONET scram-
bler/descrambler.
I
HSI automatically recovers from loss-of-clock once
its reference clock returns to normal operating state.
I
Frame alignment across multiple ORT8850 devices
for work/protect switching at OC-192/STM-64 and
above rates.
I
In-band management and configuration through
transport overhead extraction/insertion.
I
Supports transparent modes where either the only
insertion is A1/A2 framing bytes, or no bytes are
inserted.
I
Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
I
Built-in boundry scan (
IEEE
1149.1 JTAG).
I
FIFOs align incoming data across all eight channels
(two groups of four channels or four groups of two
channels) for both SONET scrambling and 8B/10B
modes. Optional ability to bypass alignment FIFOs.
I
1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for pro-
tection switching applications. STS-192 and above
rates are supported through multiple devices.
I
ORCA
FPGA soft intellectual property core support
for a variety of applications.
I
Programmable STM pointer mover bypass mode.
I
Programmable STM framer bypass mode.
I
Programmable CDR bypass mode (clocked LVDS
high-speed interface).
I
Redundant outputs and multiplexed redundant inputs
for CDR I/Os allow for implementation of eight chan-
nels with redundancy on a single device.
Embedded Core Features (Parallel)
I
Three full-duplex, double data rate (DDR) I/O groups
include 8-bit data, one control, and one clock. Each
interface is implemented with LVDS I/Os that include
on-board termination to allow long-haul driving of
backplanes, such as the industry-standard
RapidIO
interface.
I
External I/O speeds on DDR interface up to
311 MHz (622 Mbits/s per pin), with internal, single-
edge data transferred at 1/2 rate on a 32-bit bus plus
control.
I
Automatic centering of transmit clock in data eye for
DDR interface.
I
Direct interfaces to Agere Pi-Sched (266 MHz DDR
LVDS), Pi-X (128 MHz TTL), and APC (100 MHz
TTL) ATM/IP switch/port controller devices.
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ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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