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| 型號(hào)： | ORT8850H |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 29/112頁 |
| 文件大小： | 2417K |
| 代理商： | ORT8850H |
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Agere Systems Inc.
29
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Backplane Transceiver Core Detailed
Description
(continued)
The FIFO block consists of a 24-bit by 10-bit FIFO per
link. This FIFO is used to align up to ±154.3 ns of inter-
link skew and to transfer to the system clock. The FIFO
sync circuit takes metastable hardened frame pulses
from the write control blocks and produces sync signals
that indicate when the read control blocks should begin
reading from the first FIFO location. On top of the sync
signals, this block produces an error indicator which
indicates that the signals to be aligned are too far apart
for alignment (i.e., greater than 18 clocks apart). Sync
and error signals are sent to read control block for
alignment. The read control block is synched only once
on start-up; any further synchronization is software
controlled. The action of resynching a read control
block will always cause loss of data. A register allows
the read control block to be resynched.
STM Link Alignment
The general operation of the link alignment algorithm is
to wait 12 clocks (i.e., half the FIFO) from the arriving
frame pulse and then signal the read control block to
begin reading. For perfectly aligned frame pulses
across the links, it is simply a matter of counting down
12 and then signaling the read control block.
The algorithm down counts by one until all of the frame
pulses have arrived and then by two when they are all
present. For example (Figure 12), if all pulses arrive
together, then alignment algorithm would count 24
(12 clocks); if, however, the arriving pulses are spread
out over four clocks, then it would count one for the first
four pulses and then two per clock afterward, which
gives a total of 14 clocks between first frame pulse and
the first read. This puts the center of arriving frame
pulses at the halfway point in the buffer. This is the
extent of the algorithm, and it has no facility for actively
correcting problems once they occur.
The write control block receives byte-wide data at
77.76 MHz and a frame pulse two clocks before the
first A1 byte of the STS-12 frame. It generates the write
address for the FIFO block. The first A1 in every STS-
12 stream is written in the same location (address 0) in
the FIFO. Also, a frame bit is passed through the FIFO
along with the first byte before the first A1 of the STS-
12. The read control block synchronizes the reading of
the FIFO for streams that are to be aligned. Reading
begins when the FIFO sync signals that all of the appli-
cable A1s and the appropriate margin have been writ-
ten to the FIFO. All of the read blocks to be
synchronized begin reading at the same time and
same location in memory (address 0).
The alignment algorithm takes the difference between
read address and write address to indicate the relative
clock alignments between STS-12 streams. If this
depth indication exceeds certain limits (12 clocks),
then an interrupt is given to the microprocessor (align-
ment overflow). Each STS-12 stream can be realigned
by software if it gets too far out of line (this would
cause a loss of data). For background applications that
have less than 154.3 ns of interlink skew, misalignment
will not occur.
STM Link Alignment Setup
In order to ensure proper operation of the STM Link
Alignment capability, the following setup procedures
should be followed after the enabled channels have a
valid frame pulse:
1.
Put all of the streams to be aligned, including dis-
abled streams, into their required alignment mode.
2.
Force AIS-L in all streams to be synchronized
(refer to register map, write 0x01 to DB6 or register
0x30020, 0x30038, 0x30050, 0x30068, 0x30080,
0x30098, 0x300B0, and 0x300C8).
3.
Wait four frames. Write a 0x01 to the FIFO align-
ment resync register bits as required in register
0x30017 or 0x30018. Wait four frames.
4.
Release the AIS-L in all streams (write 0x00 to
DB6 or register 0x30020, 0x30038, 0x30050,
0x30068, 0x30080, 0x30098, 0x300B0, and
0x300C8). This procedure allows normal data flow
through the embedded core.
5-8584 (F)
Figure 12. Examples of Link Alignment
24-byte
FIFO
24-byte
FIFO
ALL FPs
ARRIVE
TOGETHER
(WRITING
BEGINS)
12 CLOCKS
SYNC. PULSE
(READING
BEGINS)
SYNC PULSE
(READING
BEGINS)
LAST FP
ARRIVES
4 CLOCKS
FIRST FP
ARRIVES
(WRITING
BEGINS)
10 CLOCKS
PERFECTLY ALIGNED FRAMES
4-BYTE SPREAD IN ARRIVING FRAMES
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| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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