參數(shù)資料
型號： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 36/112頁
文件大?。?/td> 2417K
代理商： ORT8850H
36
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
RapidIO
Interface to Pi-Sched
(continued)
0677
Figure 15.
RapidIO
Transmit Cell Interface
Transmit Cell Interface
The transmit interface performs multiplexing of 32 bits of low-speed data onto four sequential octets of eight pairs
of LVDS signal pins using both edges of a high-speed clock. The transmitter module consists of the following
ten LVDS signal pairs (see Figure 15):
I
Eight LVDS data pairs (TXD), double-edge clocked by the LVDS clock TXCLK. The data pairs carry biphase data
at 120 MHz
—
311 MHz.
I
One start-of-cell LVDS pair that indicates that octet 0 of a data cell is on TXD. The transitions of this signal are at
90 degrees also with the crossing points of the LVDS clock (TXCLK).
I
One LVDS clock pair output TXCLK operating at 120 MHz
—
311 MHz. Its relationship is intended to be exactly in
90 degree phase with the transitions of TXD data and TXSOC.
The high-speed data outputs (TXD[0:7]) as well as the start-of-cell signal TXSOC are generated as a result of the
positive edge of PFCLK. This is accomplished by multiplexing between the even and odd bytes of the data at a
1/2 PFCLK rate. PFCLK is derived from the internal PLL and operates at 4x the base frequency or between
240 MHz and 284 MHz. The PFCLK is expected to have a duty cycle of 47% to 53% with no more than
±
150 ps of
jitter. The duty cycle of PFCLK will directly affect the accuracy of the high-speed clock and its ability to maintain the
eye of the data. The 90 degree phase shift of the output clock puts TXCLK in the eye of the data.
COMMON
TRANSMIT
FIFO
EVEN BYTE
ODD BYTE
EVEN BYTE
UTXD
[31:0]
UTXSOC
WUTXCLK
(60 MHz
—
146 MHz)
OUTPUT
PORT CLOCK
ALIGNMENT
MUX
OUTPUT
PORT SOC
ALIGNMENT
MUX
F
PFCLK (4x OUTPUT CLOCK FROM PLL)
(240 MHz
—
584 MHz)
32 TO 8
MUX
CONTROLLER
INPUT
SOC
REGISTER
SOC
TXSOC
O
I
PLL
POSITIVE-
EDGE
FLOPS
OUTPUT
PORT DATA
ALIGNMENT
MUXes
TXCLK
TXD[7:0]
ODD BYTE
OUTPUT
PORT DATA
ALIGNMENT
MUXes
NEGATIVE-
EDGE
FLOPS
相關(guān)PDF資料
PDF描述
ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
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ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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