參數(shù)資料
型號(hào)： OX16PCI954-TQC60-A
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁(yè)數(shù)： 8/72頁(yè)
文件大小： 656K
代理商： OX16PCI954-TQC60-A
4 P
IN
D
ESCRIPTIONS
Data Sheet Revision 1.3
Page 8
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Mode
00
01
10
11
Dir
1
Name
Description
PCI interface
139, 140, 141, 143, 144, 145, 148,
149, 152, 154, 155, 156, 159, 160,
1, 2, 14, 15, 16, 19, 20, 23, 24, 26,
28, 29, 32, 33, 34, 36, 37, 38
150, 3, 13, 27
136
4
7
5
6
9
12
11
10
151
134
132,133
138
Serial port pins
46
P_I/O
AD[31:0]
Multiplexed PCI Address/Data bus
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA# INTB#
PME#
PCI Command/Byte enable
PCI systemclock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
Systemerror
Parity error
Initialization device select
PCI systemreset
PCI interrupts
Power management event
N/A
I
FIFOSEL
FIFO select. For backward compatibility with 16C550,
16C650 and 16C750 devices the UARTs’ FIFO depth is 16
when FIFOSEL is low. The FIFO size is increased to 128
when FIFOSEL is high. The unlatched state of this pin is
readable by software. The FIFO size may also be set to 128
by setting FCR[5] when LCR[7] is set, or by putting the
device into enhanced mode.
UART serial data outputs
UART IrDA data output when MCR[6] of the corresponding
channel is set in enhanced mode
UART serial data inputs
UART IrDA data input when IrDA mode is enabled (see
above)
Active-low modemdata-carrier-detect input
Active-low modemdata-termnal-ready output. If automated
DTR#flow control is enabled, the DTR#pin is asserted and
deasserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively.
In RS485 half-duplex mode, the DTR#pin may be
programmed to reflect the state of the the transmtter empty
bit to automatically control the direction of the RS485
transceiver buffer (see register ACR[4:3])
Transmtter 1x clock (baud rate generator output). For
isochronous applications, the 1x (or Nx) transmtter clock
may be asserted on the DTR#pins (see register CKS[5:4])
80, 79, 55, 54
N/A
O
SOUT[3:0]
IrDA_Out[3:0]
87, 69, 68, 47
N/A
I
I
SIN[3:0]
IrDA_In[3:0]
85, 74, 66, 49
82, 77, 59, 52
N/A
N/A
I
O
O
O
DCD[3:0]#
DTR[3:0]#
485_En[3:0]
Tx_Clk_Out[3:0]
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