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參數(shù)資料
| 型號： | OX16PCI954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁數(shù)： | 21/72頁 |
| 文件大?。?/td> | 656K |
| 代理商： | OX16PCI954 |
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Data Sheet Revision 1.3
Page 21
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
Bits
15:12
Description
Write Chip-select De-assertion (Intel-type interface). Defines the number
of clock cycles after the reference cycle when the LBCS[3:0]#pins are
de-asserted (high) during a write operation to the Local Bus.
1
Read-not-Write De-assertion during write cycles (Motorola-type
interface). Defines the number of clock cycles after the reference cycle
when the LBRDWR#pin is de-asserted (high) during a write to the Local
Bus.
1
Read Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD#pin is asserted
(low) during a read fromthe Local Bus.
1
Read Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a read fromthe Local Bus.
1
Read Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD#pin is de-
asserted (high) during a read fromthe Local Bus.
1
Read Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a read fromthe Local Bus.
1
Write Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBWR#pin is asserted
(low) during a write to the Local Bus.
1
Write Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a write to the Local Bus.
1
Write Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBWR#pin is de-
asserted (high) during a write to the Local Bus.
1
Write Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a write cycle to the Local Bus.
1
Read/Write
EEPROM
W
Reset
2h
PCI
RW
19:16
W
RW
0h
(1h for
parallel port)
23:20
W
RW
3h
(2h for
parallel port)
27:24
W
RW
0h
(1h for
parallel port)
31:28
W
RW
2h
Note 1:
Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. These parameters apply to both 8-bit and 32-bit Local Bus
configurations. See notes in the following page.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OX16PCI954-TQC60-A | Integrated Quad UART and PCI interface |
| OX4240 | OCXO |
| OX1040 | OCXO |
| OX1041 | OCXO |
| OX1042 | OCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI954_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954-TQA1G | 功能描述:外圍驅(qū)動器與原件 - PCI PCI bridge to quad serial & para. port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| OX16PCI954-TQC60-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A1 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
| OX16PCI958 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Octal UART with PCI Interface |
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