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參數(shù)資料
| 型號： | P11C68-IGDCBS |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| 中文描述： | 的CMOS / SNOS非易失性SRAM的高性能8畝× 8非易失性靜態(tài)RAM的 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 162K |
| 代理商： | P11C68-IGDCBS |
P10C68/P11C68
5
SRAM MEMORY OPERATION
Test conditions (unless otherwise stated):
Commercial and Industrial Temperature Range
Tamb = -40
°
C to + 85
°
C, Vcc = + 5V
±
10%
READ CYCLES 1 AND 2
(See note 8)
NOTES
8.
E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion. NE (bar) must be
≥
VIH during entire cycle.
For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle.
Device is continuously selected with E (bar) low, and G (bar) low.
Measured
±
200mV from steady state output voltage. Load capacitance is 5pF.
Parameter guaranteed but not tested.
9.
10.
11.
12.
t
AVAV
t
AVQV
t
AXQX
t
WHQV
ADDRESS
DQ (DATA OUT)
W
DATA VALID
Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10).
Standard
t
ELQV
t
AVAV
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
t
ELICCH
t
EHICCL
t
WHQV
Alternative
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
OHZ
t
OLZ
t
HZ
t
PA
t
PS
t
WR
Parameter
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Outout disable to output inactive
Chip enable to power active
Chip disable to power standby
Write recovery time
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
9
10
11
11
12
12
P10C68-45
P11C68-45
Min.
P10C68-35
P11C68-35
Min.
Symbol
45
5
5
0
0
Max.
45
45
25
25
20
25
55
35
5
5
0
0
Max.
35
35
20
20
15
25
45
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| P11C68-IGDPBS | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P11C68-IGDPBS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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