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參數(shù)資料
| 型號： | P11C68-IGDCBS |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| 中文描述： | 的CMOS / SNOS非易失性SRAM的高性能8畝× 8非易失性靜態(tài)RAM的 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 162K |
| 代理商： | P11C68-IGDCBS |
P10C68/P11C68
9
STORE CYCLE 2 : E (BAR) CONTROLLED
(See note 13)
Standard
t
ELQX1
t
NLEL
t
WLEL
t
ELNH
t
GHEL
Alternative
t
STORE
t
WC
Parameter
Store cycle time
NE (bar) set-up to chip enable
Write enable wet-up to chip enable
Chip enable to NE (bar) rise
Output disable set-up to E (bar) fall
Symbol
Notes
17
18
Units
ms
ns
ns
ns
ns
Min.
0
0
45
0
Max.
10
Min.
0
0
45
0
P10C68-35
P10C68-45
Max.
10
NOTES
16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion.
17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted
by Vcc <3.3V (STORE inhibit).
18. Once twc has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the store cycle is completed automatically, ignoring all
inputs. Any of NE (bar), G (bar), W (bar) or E (bar) may be used to terminate the store initiation cycle.
t
GHNL
t
NLWL
t
WLNH
t
ELWL
t
WLQX
NE
G
W
E
DQ
(DATA
OUT)
HIGH IMPEDANCE
Figure 9. STORE CYCLE 1: W (bar) controlled timing diagram (see note 16).
t
GHEL
t
NLEL
t
ELNH
t
WLEL
t
ELQX1
NE
W
E
DQ
(DATA
OUT)
HIGH IMPEDANCE
G
Figure 10. STORE CYCLE 2: E (bar) controlled timing diagram (see note 16).
相關PDF資料 |
PDF描述 |
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| P11C68-IGDPBS | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P10C68 | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P11C68-IGDPBS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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