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參數(shù)資料
| 型號(hào)： | P11C68-IGDPBS |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| 中文描述： | 的CMOS / SNOS非易失性SRAM的高性能8畝× 8非易失性靜態(tài)RAM的 |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | P11C68-IGDPBS |
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P10C68/P11C68
7
t
AVAV
t
ELWH
t
AVWH
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WHQX
t
WLQZ
t
WHAX
ADDRESS
E
W
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
F
igure 6. WRITE CYCLE 1: W (bar) controlled timing diagram (see notes 8 and 13).
Standard
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
EHAX
t
AVWL
Alternative
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
WR
t
AS
Parameter
Write cycle time
Write pulse width
Chip enable to end of write
Data set-up to end of write
Data hold after end of write
Address set-up to end of write
Address hold after end of write
Address set-up to start of write
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes
P10C68-45
P11C68-45
Min.
P10C68-35
P11C68-35
Min.
Symbol
45
35
35
30
0
35
0
0
Max.
45
35
35
30
0
35
0
0
Max.
WRITE CYCLE 2 : E (BAR) CONTROLLED
(See notes 8 and 13)
t
AVAV
t
ELEH
t
AVEL
t
EHAX
t
AVEH
t
WLEH
t
DVEH
t
EHDX
ADDRESS
E
W
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
F
igure 7. WRITE CYCLE 2: E (bar) controlled timing diagram (see notes 8 and 13).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P10C68 | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P10C68- | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P10C68-35 | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P10C68-35CG | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
| P10C68-35CGDCBS | CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM |
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