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參數(shù)資料
| 型號： | P12611EJ1V0AN00 |
| 英文描述： | MCU CMOS 28 LD 20MHZ 8K FLASH, -40C to +85C, 28-SOIC 300mil, TUBE |
| 中文描述： | uPB1509GV 1 GHz的輸入除以2。 4。 8預(yù)分頻器集成電路便攜式無線電系統(tǒng) |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 110K |
| 代理商： | P12611EJ1V0AN00 |
6
(b) S22 (Output impedance)
S22
REF 1.0 Units
200.0 mUnits/
START 0.050000000 GHz
STOP 0.350000000 GHz
Z
50 MHz
149.09
+
j14.86
350 MHz
194.21
– j36.64
(2) Divide ratio setting pins
Although this IC has a divide ratio selection function (2, 4, or, 8), it is assumed to be used with a fixed ratio.
Because of this, the divide ratio setting pins (SW1 and SW2) are designed so that they are clamped to either
high or low level unlike common prescalers. The SW1 and SW2 pins in the test circuit shown below are
connected to the external switches that clamp these pins high (connected to the V
CC1
pin) or low (connected to
the GND or leave OPEN). These external switches are provided to test the operations with all divide ratios. In
application sets that basically do not need to operate with plural ratios, however, connect each SW pin
permanently to either the V
CC1
pin or GND pattern (or left OPEN) to fix the ratio.
Therefore, it is recommended that the users specify a divide ratio when designing an application set. The
description “H level = V
CC
and L level = GND or OPEN” shown in the electrical specifications implies this
recommendation. For your reference, the following table shows the input voltages and sink current values
(design values) for the H and L levels.
Table 2-2. Design Values of Divide Ratio Setting Pins
(T
A
=
40 to +85 °C, V
CC
= 2.2 to 5.5 V, for both SW1 and SW2)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Remark
H level input voltage (SW1, SW2)
V
IH1, 2
V
CC
V
CC
+0.3
V
L level input voltage (SW1, SW2)
V
IL1, 2
GND
V
CC
1.0
V
H level sink current (SW1, SW2)
I
IH1, 2
2.1
4.4
6.4
μ
A
When T
A
= +25 °C, V
CC
= 3.0 V
L level sink current (SW1, SW2)
I
IL1, 2
0
0
0
A
However, in some application circuits, an external logic such as CMOS or TTL controls the switches. In this case,
refer to
3.3 External Control of Divide Ratio Setting Pins
.
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