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參數(shù)資料
| 型號(hào)： | P12611EJ1V0AN00 |
| 英文描述： | MCU CMOS 28 LD 20MHZ 8K FLASH, -40C to +85C, 28-SOIC 300mil, TUBE |
| 中文描述： | uPB1509GV 1 GHz的輸入除以2。 4。 8預(yù)分頻器集成電路便攜式無(wú)線電系統(tǒng) |
| 文件頁(yè)數(shù)： | 16/19頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | P12611EJ1V0AN00 |
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10
Figure 3-4. Output Amplitude vs. Load Impedance and Circuit Current Dependency
Caution
The external resistor on the output line works in the DC range if located closer than the DC-cut
capacitor to the
μ
PB1509GV. As in the test circuit, however, the external resistor located farther
than the DC-cut capacitor works in the RF range. Note that the 150
external resistor R1 on the
test circuit in Figure 2-7 is a test-purpose pseudo impedance element adjusting the load
impedance, and is not required in actual application circuits.
3.3 External Control of Divide Ratio Setting Pins
SW1 and SW2 of this IC allow users to select a divide ratio from among 2, 4, and 8. By leaving these pins OPEN
or connected to GND or V
CC1
via the mounting pattern, and whether two internal frequency dividers are enabled or
disabled, the combination of those determines a fixed divide ratio. On the other hand, some user’s applications may
need to switch divide ratio – from 2 to 4 and vice versa, for example – according to the input frequency changes.
However, since the divide ratio of this IC is not intended to be controlled by external ratio switching logics, the low-
level range of SW pins themselves is wide and the high-level range is narrow. (Refer to
Table 2-2. Design Values
of Divide Ratio Setting Pins
.) Therefore, it is difficult to change the divide ratio by controlling the voltage applied to
these pins from a simply connected CMOS logic because the threshold voltage of SW pins is V
CC
– 1.0 V to V
CC
(V).
To adjust this H/L threshold level, connect external resistors to the SW pins as shown in Figure 3-5 for example,
where a pull-up resistor and a series resistor are externally connected. These external resistors and the internal
elements together configure the switching circuit. The control voltage range with the external resistors is shown in
Table 3-2.
Figure 3-5. Application Circuit Example for Divide Ratio Control Voltage Range Adjustment by Connecting
External Resistors to SW Pin
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00
2
4
6
8
Circuit current due to pull-down resistor I
CC
(mA)
10
12
14
16
O
O
(
P
)
1
T
A
= +25 C. V
CC
= 3.0 V
f
in
= 408 MHz. P
in
= –20 dBm
Divide ratio ÷ 4
Z
L
= 1250
Z
L
= 200
Z
L
= 50
V
CC1
SW
C1
IC
20 k
3 k
From power supply
V
IH
or V
IL
To divider
2 or 3
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