參數(shù)資料
型號: P12763EJ1V0AN00
英文描述: MCU CMOS 28 LD 20MHZ 8K FLASH, -40C to +85C, 28-SPDIP, TUBE
中文描述: uPC8119T和uPC8120T可變增益高頻硅單片放大器的AGC移動通信股
文件頁數(shù): 8/19頁
文件大小: 159K
代理商: P12763EJ1V0AN00
8
Figure 3-1. Cross-Sectional View of Transistor Created by NESAT Process (internal element of IC)
Collector
Base
Emitter
Electrode
Oxide film
Epitaxial layer
n
+
layer
Substrate
P-channel stopper
Polysilicon
Nitride film
P
P
P
n
n
n
+
4. INTERNAL CIRCUIT CONFIGURATION AND OPERATION
Figure 4-1 shows the internal equivalent circuit of the
P
PC8119T and
P
PC8120T. The internal circuits of the
P
PC8119T and
P
PC8120T are identical except for the internal control circuit.
Both the
P
PC8119T and
P
PC8120T are differential amplifiers and vary the gain by changing the current proportion
of the differential transistor pairs of control circuit side and output side. The output pins are of the open-collector of
the output transistor and externally configure a matching circuit. The same voltage as V
CC
is applied to the output pin
as a bias via the inductor of the matching circuit. The circuit current is the sum of the current into V
CC
pin and into the
output pin. Although the proportion of these circuit current changes with the control voltage, the sum of the current
into the output pin and into the V
CC
pin is constant. The current into the V
CC
pin is minimum at the maximum gain,
and maximum at the minimum gain (at maximum attenuation). Conversely, the current into the output pin is
maximum at the maximum gain, and minimum at the minimum gain (at maximum attenuation). To get maximum gain,
AGC control voltage should be minimized on
P
PC8119T of forward control type but should be maximized on
P
PC8120T of reverse control type. (Refer to the
characteristic curves
in
Data Sheet
.) The explanation here can be
summarized in the Table 4-1.
Figure 4-1. Equivalent Circuit of Internal Block
Differential amplifier
Control voltage input block
1
2
3
5
4
To bias circuit
From gain
control block
To gain control block
2
3
5
6
Remark
The gain control block is not described at element level because the internal design of the IC is confidential.
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