參數(shù)資料
型號(hào)： P80C557E6
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller(單片8位微控制器)
中文描述： 單芯片8位微控制器（單片8位微控制器）
文件頁(yè)數(shù)： 41/64頁(yè)
文件大?。?/td> 476K
代理商： P80C557E6
Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
41
Table 40.
External Pin Status During Idle and Power-Down Modes
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
SCL/SDA
PWM0/PWM1
Idle
Internal
1
1
data
data
data
data
data
operative (1)
HIGH
Idle
External
1
1
high – Z
data
address
data
data
operative (1)
HIGH
Power-down
Internal
0
0
data
data
data
data
data
high–Z
HIGH
Power-down
NOTE:
1. In Idle Mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0) these pins are in a
high–impedance state.
External
0
0
high – Z
data
data
data
data
high–Z
HIGH
Clock
Gen.
Interrupts,
Serial
Ports,
T0, T1, T3
XTAL4
XTAL3
Figure 40. Idle and Power Down Hardware for Clock Generation
XTAL1
XTAL2
3.5 to
16 MHz
Osc
f
CLK
CPU
T2
ADC
PWM
32 kHz
PLL
Osc
Seconds timer
PD
IDL
SELXTAL1
6.11.3
The instruction that sets PCON.1 is the last executed prior to going
into the Power-down Mode. Once in Power-down Mode, the HF
oscillator is stopped. The 32 kHz oscillator may stay running. The
content of the on-chip RAM and the Special Function Registers are
preserved. Note that the Power-down Mode can not be entered
when the watchdog has been enabled.
Power-down Mode
The Power-down Mode can be terminated by an external RESET in
the same way as in the 80C51 (RAM is saved, but SFRs are cleared
due to RESET) or in addition by any one of the external interrupts
(INT0, INT1) or Seconds interrupt.
The status of the external pins during Power-down Mode is shown in
Table 40. If the Power-down Mode is activated while in external
program memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the data is a logic1, the port pin
is held HIGH during the Power-down Mode by the strong pull-up
transistor P1 (see Figure 9).
The Power-down Mode should not be entered within an interrupt
routine because Wake-up with an external or ‘Seconds’ interrupt is
not possible in that case.
6.11.4
The Power-down Mode of the P8xC557E6 can also be terminated
by any one of the three enabled interrupts, INT0, INT1 or Seconds
interrupt.
Wake-up from Power-down Mode
If there is an interrupt already in service, which has same or higher
priority as the Wake-up interrupt, Power-down Mode will switch over
to Idle Mode and stay there until an interrupt of higher priority
terminates Idle Mode.
A termination with these interrupts does not affect the internal data
memory and does not affect the Special Function Registers. This
gives the possibility to exit Power-down without changing the port
output levels. To terminate the Power-down Mode with an external
interrupt, INT0 or INT1 must be switched to be level-sensitive and
must be enabled. The external interrupt input signal INT0 or INT1
must be kept LOW till the oscillator has restarted and stabilized (see
Figure 41). A Seconds interrupt will terminate the Power-down Mode
if it is enabled and INT1 is level sensitive. In order to prevent any
interrupt priority problems during Wake-up, the priority of the desired
Wake-up interrupt should be higher than the priorities of all other
enabled interrupt sources.
The instruction following the one that put the device into the
Power-down Mode will be the first one which will be executed after
the interrupt routine has been serviced.
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