參數(shù)資料
型號(hào)： P80C557E6
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller(單片8位微控制器)
中文描述： 單芯片8位微控制器（單片8位微控制器）
文件頁(yè)數(shù)： 46/64頁(yè)
文件大?。?/td> 476K
代理商： P80C557E6
Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
46
7.
The P8xC557E6 uses the powerful instruction set of the PCB80C51.
It consists of 49 single–byte, 45 two–byte and 17 three–byte
instructions. Using a 16 MHz quartz, 64 of the instructions are
executed in 0.75
μ
s, 45 in 1,5
μ
s and the multiply, divide instructions
in 3
μ
s.
INSTRUCTION SET
A summary of the instruction set is given in Table 43.
The P8xC557E6 has additional Special Function Registers to
control the on–chip peripherals.
7.1
Most instructions have a “destination, source” field that specifies the
data type, addressing modes and operands involved. For all these
instructions, except for MOVs, the destination operand is also the
source operand (e.g., ADD A,R7).
Addressing Modes
There are five kinds of addressing modes:
Register Addressing
–
R0 – R7 (4 banks)
–
A,B,C (bit), AB (2 bytes), DPTR (double byte)
Direct Addressing
–
lower 128 bytes of internal Main RAM
(including the 4 R0–R7 register banks)
–
Special Function Registers
–
128 bits in a subset of the internal Main RAM
–
128 bits in a subset of the Special Function Registers
Register–Indirect Addressing
–
internal Main RAM (@R0, @R1, @SP [PUSH/POP])
–
internal Auxiliary RAM (@R0, @R1, @DPTR)
–
external Data Memory (@R0, @R1, @DPTR)
Immediate Addressing
–
Program Memory (in–code 8 bit or 16 bit constant)
Base–Register–plus Index–Register–Indirect Addressing
–
Program Memory look–up table (@DPTR+A, @PC+A)
The first three addressing modes are usable for destination
operands.
7.1.1
80C51 Family Instruction Set
Table 42.
Instruction that affect Flag settings
1
INSTRUCTION
FLAG
C
OV
AC
ADD
ADDC
SUBB
MUL
DIV
DA
RRC
RLC
SETB C
X
X
X
0
0
X
X
X
1
X
X
X
X
X
X
X
X
X
CLR C
CPL C
ANL C, bit
ANL C,/bit
ANL C, bit
ORL C, bit
MOV C, bit
CJNE
0
X
X
X
X
X
X
X
NOTE:
1. Note that operations on SFR byte address 208 or bit addresses
209-215 (i.e., the PSW or bits in the PSW) will also affect flag
settings.
Notes on instruction set and addressing modes:
Rn
Register R7-R0 of the currently selected Register
Bank.
direct
8-bit internal data location’s address. This could be
an Internal Data RAM location (0-127) or a SFR
[i.e., I/O port, control register, status register, etc.
(128-255)].
@Ri
8-bit RAM location addressed indirectly through reg-
ister R1 or R0 of the actual register bank.
#data
8-bit constant included in the instruction.
#data 16
16-bit constant included in the instruction
addr 16
16-bit destination address. Used by LCALL and
LJMP. A branch can be anywhere within the 64
Kbytes Program Memory address space.
addr 11
11-bit destination address. Used by ACALL and
AJMP. The branch will be within the same 2 Kbytes
page of program memory as the first byte of the fol-
lowing instruction.
rel
Signed (two’s complement) 8-bit offset byte. Used by
SJMP and all conditional jumps. Range is –128 to
+127 bytes relative to first byte of the following
instruction.
bit
Direct Addressed bit in Internal Data RAM or Special
Function Register.
Hexadecimal opcode cross-reference to Table 43
*
:
8, 9, A, B, C, D, E. F.
**
:
11, 31, 51, 71, 91, B1, D1, F1.
***
:
01, 21, 41, 61, 81, A1, C1, E1.
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