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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
43
6.13.2
A current controlled oscillator (CCO) generates a clock frequency
f
CCO
of approx. 32 , 38 , 44 or 50 MHz , controlled by the PLL, with
the 32kHz oscillator as the reference clock. The system clock
frequency f
CLK
can be varied under software control by changing the
contents of the PLL control register (PLLCON):
PLL CCO
f
CCO
can be changed via the PLLCON bits FSEL(1:0)
(see Table 41). The maximum locking time is 10 ms
(2)
.
During the stabilization phase, no time critical routines should be
executed.
The system clock frequency f
CLK
is derived from f
CCO
under control
of the PLLCON bits FSEL(4:0) (see Table 41).
If only FSEL(4:2) is changed but not FSEL(1:0), then it takes about
1us until the new frequency is available.
Changing the system clock frequency has to be done in two steps.
From HIGH to LOW frequencies:
First change (FSEL(4:2), then FSEL (1:0).
From LOW to HIGH frequencies:
First change only FSEL (1:0) and after a stabilization phase of
10 ms change FSEL (4:2).
6.13.3
PLLCON is a special function register, which can be read and
written by software. It contains the control bits:
to select one of several system clock frequencies (see Table 41)
the seconds interrupt flag: SECINT
to enable the seconds interrupt flag: ENSECI
the RUN32 bit, which defines if during Power–down Mode the
32kHz oscillator is halted or stays running .
PLL Control Register – PLLCON
PLLCON is initialized to 0DH upon Reset (RSTIN = ‘1’) or Watchdog
Timer Overflow. PLLCON = 0DH corresponds to a system clock
frequency of 11.01 MHz.
Figure 44. PLL control register (PLLCON).
7
6
5
4
3
2
1
0
PLLCON (F9H)
RUN32
ENSECI
SECINT
FSEL.4
FSEL.3
FSEL.2
FSEL.1
FSEL.0
Table 41.
PLLCON
SYMBOL
BIT
FUNCTION
RUN32
PLLCON.7
RUN32 = 0: The 32 kHz oscillator halts during Power–down.
RUN32 = 1: The 32 kHz oscillator stays running during Power–down.
ENSECI
PLLCON.6
Enable the seconds interrupt.
(enabling INT1 is also required)
SECINT
PLLCON.5
Seconds interrupt requested by an overflow of the seconds timer (which occurs every second) or via writing
a ‘1’ to this bit.
SECINT can only be cleared by writing a ‘0’ to this bit .
FSEL.4
PLLCON.4
System clock frequency in MHz
to
FSEL.0
to
PLLCON.0
11
FSEL[1:0]10
01
00
15.73
7.86
9.44
11.01
12.58
3.93
4.72
5.51
6.29
010
011
100
FSEL[4:2]
Other combinations, than mentioned above, are reserved and may not be selected .
This allows to generate the standard baudrates 19200, 9600, 4800, 2400 and 1200 Baud , when using the UART and Timer1.
2.
This parameter is characterized.