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參數(shù)資料
| 型號： | P83C834 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontrollers with LCD-driver |
| 中文描述： | 8位微控制器與LCD驅(qū)動器 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 165K |
| 代理商： | P83C834 |
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1997 Jul 03
8
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
6
FUNCTIONAL DESCRIPTION
The block diagram is shown in Fig.1. The P83C434 and
P83C834 provide all functions that are required for a user
interface. This is illustrated in the radio application detailed
in Chapter 12. In the following sections the functions of the
device are described.
6.1
Input/Output (I/O)
A total of 12 I/O lines are available.
Port 0 P0.0 to P0.7 (8 lines).
Port configuration: Quasi-bidirectional (push-pull in
emulation mode). For the Interrupt generation see
Fig.10. If one of the port lines P0.0 to P0.3 is a
logic 0 or one of the port lines P0.4 to P0.7 is equal
to the corresponding bit in the Miscellaneous
Control Register (MCON) and the corresponding bit
in the Interrupt Gate Register (IG) is a logic 1, then
an INT0 interrupt is generated.
Port 2 P2.0 to P2.3 (4 lines).
Port configuration: Quasi-bidirectional (push-pull in
emulation mode). When writing to Port 2, bits
P2.4 to P2.7 have to be fixed at HIGH. Data to be
written should be ‘1111
XXXX
B’.
6.1.1
EMC (E
LECTROMAGNETIC
C
OMPATIBILITY
)
In order to reduce EMI (Electromagnetic Interference) the
following design measures have been taken:
Slope control is implemented on all the I/O lines.
Rise and fall time (10% to 90%) are:
20 ns < rise/fall time < 50 ns.
The power supply and ground pins are placed next to
each other.
Double bonding V
SS
pins, i.e. 2 bondpads for each pin.
Limiting the drive capability of:
– clock drivers and prechargers.
– segment drivers and backplane drivers for the LCD.
External decoupling of the of the CPU supply V
DD(C)
;
to avoid interference on the V
DD
line, the V
DD(C)
and
V
DD(P)
pins should be connected as illustrated in Fig.4.
Fig.4 Avoiding interference on V
DD
.
handbook, halfpage
MGG019
P83C434
P83C834
VDD(C)
VDD
VDD(P)
2.2
μ
H
Fig.5 Standard output with switched pull-up current source.
handbook, full pagewidth
MLC926 - 1
p1
p2
p3
input data
read port pin
2 oscillator
periods
n
strong pull-up
I/O PIN
V
I1
Q
from port latch
INPUT
BUFFER
DD
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