參數(shù)資料
型號(hào)： P83CE598FHB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit microcontroller with CAN controller(帶CAN控制器的8位微控制器)
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 27/108頁(yè)
文件大小： 661K
代理商： P83CE598FHB
1996 Jun 27
27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
11.3
Watchdog Timer (T3)
In addition to Timer T2 and the standard timers (Timer 0
and Timer 1), a Watchdog Timer (WDT) comprising an
11-bit prescaler and an 8-bit timer (T3) is also provided
(see Fig.12).
The timer T3 is incremented every 1.5 ms, derived from
the oscillator frequency of 16 MHz by the following
f
12
2048
×
formula:
When a timer T3 overflow occurs, the microcontroller is
reset and a reset-output-pulse is generated at pin RST.
This short output pulse (3 machine cycles) may be
suppressed if the RST pin is connected to a capacitor.
To prevent a system reset (by an overflow of the WDT), the
user program has to reload T3 within periods that are
shorter than the programmed Watchdog time interval.
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the
processor running out of control.
f
timer
-------------------------
=
The Watchdog Timer can only be reloaded if the condition
flag WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The timer interval between the timer's reloading and the
occurrence of a reset depends on the reloaded value. For
example, this may range from 1.5 ms to 0.375 s when
using an oscillator frequency of 16 MHz.
In the Idle state the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer (WDT) is controlled by the Enable
Watchdog pin (EW); see Table 28.
Table 28
EW controlling WDT and Power-down mode
PIN EW
WDT
POWER-DOWN MODE
LOW
HIGH
enabled
disabled
disabled
enabled
Fig.12 Functional diagram of T3 Watchdog Timer.
handbook, full pagewidth
MGA157
INTERNAL BUS
1/12 fCLK
write
T3
PRESCALER
11-BIT
TIMER T3 (8-BIT)
LOAD
CLEAR
overflow
internal
reset
LOADEN
EW
LOADEN
PCON.4
PCON.1
CLEAR
WLE
PD
RRST
RST
P
VDD
INTERNAL BUS
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