參數(shù)資料
型號(hào)： P83CE598FHB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit microcontroller with CAN controller(帶CAN控制器的8位微控制器)
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 47/108頁
文件大?。?/td> 661K
代理商： P83CE598FHB
1996 Jun 27
47
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.12 T
EST
R
EGISTER
(TR)
The Test Register is used for production testing only.
Table 53
Test Register (address 9)
13.5.13 T
RANSMIT
B
UFFER LAYOUT
The global layout of the Transmit Buffer is shown in Fig.15. This buffer serves to store a message from the CPU to be
transmitted by the CAN-controller. It is subdivided into Descriptor and Data Field. The Transmit Buffer can be written to
and read from by the CPU.
13.5.13.1 Descriptor
Table 54
Descriptor Byte 1 Register (DSCR1, address 10)
Table 55
Descriptor Byte 2 Register (DSCR2, address 11)
Table 56
Description of the ID.n bits in DSCR1 and DSCR2
7
6
5
4
3
2
1
0
Reserved
Reserved
Map Internal
Register
Connect RX
Buffer 0
CPU
Connect TX
Buffer CPU
Access
Internal Bus
Normal
RAM
Connect
Float Output
Driver
7
6
5
4
3
2
1
0
ID.10
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
7
6
5
4
3
2
1
0
ID.2
ID.1
ID.0
RTR
DLC.3
DLC.2
DLC.1
DLC.0
BIT
SYMBOL
FUNCTION
DSCR1
7
6
5
4
3
2
1
0
ID.10
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
Identifier.
The Identifier consists of 11 bits (ID.10 to ID.0). ID.10 is the most significant
bit, which is transmitted first on the bus during the arbitration process. The Identifier acts
as the messages' name, used in a receiver for acceptance filtering, and also determines
the bus access priority during the arbitration process. The lower the binary value of the
Identifier the higher the priority. This is due to the larger number of leading dominant bits
during arbitration (see Section 13.6.7).
DSCR2
7
6
5
ID.2
ID.1
ID.0
Identifier
. See DSCR1.
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