參數(shù)資料
型號(hào)： P83CL782HDH
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low voltage 8-bit microcontrollers with UART and I2C-bus
中文描述： MROM, 6 MHz, MICROCONTROLLER, PQFP44
封裝： 14 X 14 MM, 2.20 MM HEIGHT, PLASTIC, SOT-205-1, QFP-44
文件頁(yè)數(shù)： 25/76頁(yè)
文件大小： 342K
代理商： P83CL782HDH
1997 Mar 14
25
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I
2
C-bus
P83CL781; P83CL782
13.1
Serial Control Register (S1CON)
Table 7
Serial Control Register (SFR address D8H)
Table 8
Description of S1CON bits
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
BIT
SYMBOL
DESCRIPTION
7
CR2
This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock
frequency when SIO is in the Master mode. See Table 9.
ENABLE serial I/O
. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs
are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.
START flag
. When this bit is set in Slave mode, the SIO hardware checks the status of
the I
2
C-bus and generates a START condition if the bus is free or after the bus becomes
free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START
condition.
STOP flag
. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the I
2
C-bus, the SIO hardware clears the STO flag.
STO may also be set in Slave mode in order to recover from an error condition. In this
case no STOP condition is transmitted to the I
2
C-bus. However, the SIO hardware
behaves as if a STOP condition has been received and releases the SDA and SCL. The
SIO then switches to the not addressed slave receiver mode. The STOP flag is cleared
by the hardware.
SIO interrupt flag
. This flag is set, and an interrupt is generated, after any of the
following events occur:
A start condition is generated in Master mode
Own slave address has been received during AA = 1
The general call address has been received while GC (S1ADR.0) = 1 and AA = 1
A data byte has been received or transmitted in Master mode (even if arbitration is lost)
A data byte has been received or transmitted as selected slave
A Stop or Start condition is received as selected slave receiver or transmitter.
Assert Acknowledge
. When this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
Own slave address is received
General call address is received; GC (S1ADR.0) = 1
A data byte is received while the device is programmed to be a Master Receiver
A data byte is received while the device is a selected Slave Receiver.
When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency
when SIO is in the Master mode. See Table 9.
6
ENS1
5
STA
4
STO
3
SI
2
AA
1
0
CR1
CR0
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