參數(shù)資料
型號(hào)： P83CL782HDH
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Low voltage 8-bit microcontrollers with UART and I2C-bus
中文描述： MROM, 6 MHz, MICROCONTROLLER, PQFP44
封裝： 14 X 14 MM, 2.20 MM HEIGHT, PLASTIC, SOT-205-1, QFP-44
文件頁(yè)數(shù)： 61/76頁(yè)
文件大小： 342K
代理商： P83CL782HDH
1997 Mar 14
61
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART and I
2
C-bus
P83CL781; P83CL782
Notes
1.
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output
voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise
is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW
transitions during bus operations. In the most adverse conditions (capacitive loading
>
100 pF), the noise pulse on
the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an
address latch with a Schmitt trigger strobe input.
Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall
below the 0.9% of V
DD
specification when the address bits are stabilizing.
Circuits with Power-on reset option ‘OFF’ are tested at V
DDmin
= 1.8 V; with the ‘ON’ option (typically 1.3 V) they are
tested at V
DDmin
= 2.3 V.
The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
=10 ns;
V
IL
= V
SS
; V
IH
= V
DD
; XTAL2 not connected; EA = RST = Port 0 = V
DD
.
The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 10 ns;
V
IL
= V
SS
; V
IH
= V
DD
; XTAL2 not connected; EA = Port 0 = V
DD
.
The Power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = V
DD
;
RST = V
SS
.
The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I
2
C-bus specification. Therefore, an input voltage
below 0.3V
DD
will be recognized as a logic 0 and an input voltage above 0.7V
DD
will be recognized as a logic 1.
2.
3.
4.
5.
6.
7.
Inputs
V
IL
V
IH
I
IL
LOW level input voltage
HIGH level input voltage
LOW level input current
note 7
note 7
V
DD
= 5 V; V
IN
= 0.4 V; note 7
V
DD
= 2.5 V; V
IN
= 0.4 V; note 7
V
DD
= 5 V; V
IN
= 0.5V
DD
; note 7
V
DD
= 2.5 V; V
IN
= 0.5V
DD
; note 7
V
SS
<
V
I
<
V
DD
; note 7
V
SS
0.7V
DD
0.3V
DD
V
V
DD
100
50
1.0
500
±
10
V
μ
A
μ
A
mA
μ
A
μ
A
I
IL(T)
LOW level input current
(HIGH-to-LOW transition)
I
LI
Outputs
input leakage current
I
OL
LOW level output current;
except SDA and SCL
V
DD
= 5 V; V
OL
= 0.4 V
V
DD
= 2.5 V; V
OL
= 0.4 V
V
DD
= 5 V; V
OL
= 0.4 V
1.6
0.7
3.0
mA
mA
mA
I
OL1
LOW level output current; SDA
and SCL
HIGH level output current
(push-pull options only)
I
OH
V
DD
= 5 V; V
OH
= V
DD
0.4 V
V
DD
= 2.5 V; V
OH
= V
DD
0.4 V
1.6
0.7
10
200
mA
mA
k
R
RST
RST pull-down resistor
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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