參數(shù)資料
型號(hào)： P89LPC9321FN,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 11/71頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 28-DIP
產(chǎn)品培訓(xùn)模塊： LPC9351/9321 Overview
標(biāo)準(zhǔn)包裝： 13
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.600"，15.24mm）
包裝： 管件
配用： 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱： 568-4700-5
935287657112
P89LPC9321FN
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[1]
All ports are in input only (high-impedance) state after power-up.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3]
The RSTSRC register reflects the cause of the P89LPC9321 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is x011 0000.
[4]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5]
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog
feed 1
C2H
WFEED2
Watchdog
feed 2
C3H
Table 4.
Special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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