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參數(shù)資料
| 型號(hào)： | P89LPC9321FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 16/71頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 28-DIP |
| 產(chǎn)品培訓(xùn)模塊： | LPC9351/9321 Overview |
| 標(biāo)準(zhǔn)包裝： | 13 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 622-1003-ND - KIT FOR LCD DEMO 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY |
| 其它名稱： | 568-4700-5 935287657112 P89LPC9321FN |
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P89LPC9321
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 16 November 2010
23 of 71
NXP Semiconductors
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
7.10 CCLK wake-up delay
The P89LPC9321 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus
60
μsto100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to
300
μs. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
Fig 6.
Block diagram of oscillator control
÷2
002aae108
RTC
CPU
WDT
DIVM
CCLK
UART
OSCCLK
I2C-BUS
PCLK
TIMER 0 AND
TIMER 1
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC OSCILLATOR
WITH CLOCK DOUBLER
WATCHDOG
OSCILLATOR
(7.3728 MHz/14.7456 MHz
± 1 %)
PCLK
RCCLK
SPI
CCU
32
× PLL
(400 kHz
± 5 %)
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相關(guān)代理商/技術(shù)參數(shù) |
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| P89LPC932A1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM |
| P89LPC932A1FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-Bit Microcontroller with accelerated two-clock 80C51 core 8kB 3V byte-erasable flash with 512-byte data EEPROM |
| P89LPC932A1FA,112 | 功能描述:8位微控制器 -MCU 8K FL/768B RAM/512B EE/CCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC932A1FA,129 | 功能描述:8位微控制器 -MCU 8K FL/768B RAM/512B EE/CCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC932A1FDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM |
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