參數(shù)資料
型號: P89LPC952FA,512
廠商: NXP Semiconductors
文件頁數(shù): 19/69頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 44-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 26
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1016-ND - BOARD FOR P89LPC952FA 44-PLCC
622-1008-ND - BOARD FOR LPC9103 10-HVSON
OM10075-ND - EVAL BOARD FOR LPC952
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2253-5
935280148512
P89LPC952FA
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
26 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.10 Memory organization
The various P89LPC952/954 memory spaces are as follows:
DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip
XDATA memory, plus extended SFRs located in XDATA.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC952/954 has 8 kB/16 kB of on-chip Code memory.
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
7.12 Interrupts
The P89LPC952/954 uses a four priority level interrupt structure. This allows great
exibility in controlling the handling of the many interrupt sources. The P89LPC952/954
supports 17 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port 0 TX,
serial port 0 RX, combined serial port 0 RX/TX, serial port 1 TX, serial port 1 RX,
combined serial port 1 RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard,
comparators 1 and 2, SPI, and ADC completion.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0, IEN1 or IEN2. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Table 6.
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
XDATA
Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions
256
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