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參數(shù)資料
| 型號： | PC7447VGH1200N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 6/66頁 |
| 文件大?。?/td> | 522K |
| 代理商： | PC7447VGH1200N |
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6
PC7457/47 [Preliminary]
5345B–HIREL–02/04
Performs alignment, normalization, and precision conversion for floating-
point data
Executes cache control and TLB instructions
Performs alignment, zero padding, and sign extension for integer data
Supports hits under misses (multiple outstanding misses)
Supports both big- and little-endian modes, including misaligned little-endian
accesses
Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three
instructions, respectively, in a cycle. Instruction dispatch requires the following:
–
Instructions can be dispatched only from the three lowest IQ entries – IQ0,
IQ1, and IQ2
–
A maximum of three instructions can be dispatched to the issue queues per
clock cycle
–
Space must be available in the CQ for an instruction to dispatch (this
includes instructions that are assigned a space in the CQ but not in an issue
queue)
Rename buffers
–
16 GPR rename buffers
–
16 FPR rename buffers
–
16 VR rename buffers
Dispatch unit
–
Decode/dispatch stage fully decodes each instruction
Completion unit
–
The completion unit retires an instruction from the 16-entry completion
queue (CQ) when all instructions ahead of it have been completed, the
instruction has finished execution, and no exceptions are pending
–
Guarantees sequential programming model (precise exception model)
–
Monitors all dispatched instructions and retires them in order
–
Tracks unresolved branches and flushes instructions after a mispredicted
branch
–
Retires as many as three instructions per clock cycle
Separate on-chip L1 Instruction and data caches (Harvard Architecture)
–
32 Kbyte, eight-way set-associative instruction and data caches
–
Pseudo least-recently-used (PLRU) replacement algorithm
–
32-byte (eight-word) L1 cache block
–
Physically indexed/physical tags
–
Cache write-back or write-through operation programmable on a per-page or
per-block basis
–
Instruction cache can provide four instructions per clock cycle; data cache
can provide four words per clock cycle
–
Caches can be disabled in software
–
Caches can be locked in software
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PC7447VGH933L | PowerPC 7457 RISC Microprocessor |
| PC7447VGH933N | PowerPC 7457 RISC Microprocessor |
| PC7457 | PowerPC 7457 RISC Microprocessor |
| PC7457MGU1000L | PowerPC 7457 RISC Microprocessor |
| PC7457MGU1000N | PowerPC 7457 RISC Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC7447VGH933L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7447VGH933N | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 7457 RISC Microprocessor |
| PC7448FGH1267ND | 制造商:e2v technologies 功能描述:PC7448FGH1267ND - Trays |
| PC7448MGH1000ND | 制造商:e2v technologies 功能描述:PC7448MGH1000ND - Trays |
| PC7448MGH1250ND | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
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