參數(shù)資料
型號: PC7457VGU1000N
廠商: Atmel Corp.
英文描述: PowerPC 7457 RISC Microprocessor
中文描述: 7457的PowerPC RISC微處理器
文件頁數(shù): 3/66頁
文件大?。?/td> 522K
代理商: PC7457VGU1000N
3
P
5
B
F
P
+
(3)
+
IIInteger
UUnit 2
SStation
Additional Features
- Time Base Counter/Decrementer
- Clock Multiplier
- JTAG/COP Interface
- Thermal/Power Management
- Performance Monitor
PA
Instruction Unit
Instruction Queue
(12-Word)
96-Bit (3 Instructions)
Reservation
Stations (2)
128-Bit (4 Instructions)
32-Bit
FPSCR
+ x ÷
Floating-
Point Unit
64-Bit
Reservation
Stations (2-Entry)
32-Bit
Completion Unit
Completion Queue
(16-Entry)
32-Kbyte
D Cache
36-Bit
Address Bus
64-Bit
Data Bus
Reservation
Stations (2)
FPR File
16 Rename
Buffers
GPR File
16 Rename
Buffers
Reservation
Station
VR File
16 Rename
Buffers
64-Bit
128-Bit
Completes up
to three
instructions
Instruction MMU
SRs
128-Entry
ITLB
IBAT Array
Tags
32-Kbyte
I Cache
Vector
Touch
Queue
VR Issue
(4-Entry/2-Issue)
FPR Issue
(2-Entry/1-Issue)
Branch Processing Unit
CTR
LR
BTIC (128-Entry)
BHT (2048-Entry)
Fetcher
GPR Issue
(6-Entry/3-Issue)
Dispatch
Unit
Data MMU
SRs
(Original)
128-Entry
DTLB
DBAT Array
32-Bit
EA
Status
L2 Store Queue (L2SQ)
L1 Castouts
(4)
Vector
FPU
Reservation
Station
Reservation
Station
Reservation
Station
Vector
Integer
Unit 1
Vector
Integer
Unit 2
Vector
Permute
Unit
Line
Tags
Block 0 (32-Byte)
Status
Block 1 (32-Byte)
Memory Subsystem
Snoop Push/
Interventions
Bus Accumulator
x ÷
Integer
Unit 2
per clock
L1 Load Queue (LLQ)
L1 Load Miss (5)
Cacheable Store Request(1)
L1 Service
Queues
L1 Store Queue
(LSQ)
L3 Cache Controller(1)
L3CR
Status
Tags
Bus Accumulator
Block 0/1
Line
System Bus Interface
L2 Prefetch (3)
64-Bit Data
(8-Bit Parity)
External SRAM
(1, 2, or 4 Mbytes)
Castout
Queue (9)/
Bus Store Queue
Push
Load
Queue (11)
Notes:
1. The L3 cache interface is not implemented on the PC7447.
2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.
The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
512-Kbyte UniTed L2 Cache Controller
19-Bit Address
Tags
Instruction Fetch (2)
128-Bit
RReservation
(Shadow)
+
Load/Store Unit
Vector Touch Engine
(EA Calculation)
Finished
Stores
Completed
Stores
Load Miss
L1 Castout
L1 Push
+
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