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| 型號： | PC7457VGU1000N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 32/66頁 |
| 文件大小： | 522K |
| 代理商： | PC7457VGU1000N |
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32
PC7457/47 [Preliminary]
5345B–HIREL–02/04
L3 Bus AC Specifications for
PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be con-
nected as shown in Figure 15 on page 33. These SRAMs are synchronous to the
PC7457; one L3_CLKn signal is output to each SRAM to latch address, control, and
write data. Read data is launched by the SRAM synchronous to the delayed L3_CLKn
signal it received. The PC7457 needs a copy of that delayed clock which launched the
SRAM read data to know when the returning data will be valid. Therefore,
L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and then
returned to the PC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively.
Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock
received at the SRAMs. The PC7457 will latch the incoming data on the rising edge of
L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14 provides the L3 bus interface AC timing specifications for the configuration
shown in Figure 15, assuming the timing relationships of Figure 16 and the loading of
Figure 12 on page 26.
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
DD
.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50
load (see Figure
14).
5. t
L3_CLK
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
by an internal clock delayed in phase by 90
°
. Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
6. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27 for more
information.
Table 14.
L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating Condi-
tions (see Table 3 on page 12)
Symbol
Parameter
All Speed Grades
Unit
Min
Max
t
L3CR
, t
L3CF
L3_CLK rise and fall time
(1)(2)
–
0.75
ns
t
L3DVEH
Setup times: Data and parity
(2)(3)
0.1
–
ns
t
L3DXEH
Input hold times: Data and parity
(2)(3)
–
0.7
ns
t
L3CHDV
Valid times: Data and parity
(2)(4)(5)(6)
–
2.5
ns
t
L3CHOV
Valid times: All other outputs
(5)(6)
–
1.8
ns
t
L3CHDX
Output hold times: Data and parity
(2)(4)(5)(6)
1.4
–
ns
t
L3CHOX
Output hold times: All other outputs
(2)(5)(6)
1.0
–
ns
t
L3CHDZ
L3_CLK to high impedance: Data and parity
(2)
–
3.0
ns
t
L3CHOZ
L3_CLK to high impedance: All other outputs
(2)
–
3.0
ns
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相關代理商/技術參數(shù) |
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