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參數(shù)資料
| 型號： | PC7457VGU933N |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7457 RISC Microprocessor |
| 中文描述： | 7457的PowerPC RISC微處理器 |
| 文件頁數(shù)： | 29/66頁 |
| 文件大?。?/td> | 522K |
| 代理商： | PC7457VGU933N |
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29
PC7457/47 [Preliminary]
5345B–HIREL–02/04
These CQ clocks are received on the L3_ECHO_CLKn inputs of the PC7457. An inter-
nal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within
the valid data window at the internal receiving latches. This delayed clock is used to
capture the data into these latches which comprise the receive FIFO. This clock is asyn-
chronous to all other processor clocks. This latched data is subsequently read out of the
FIFO synchronously to the processor clock. The time between writing and reading the
data is set by using the sample point settings defined in the L3CR register.
Table 13 provides the L3 bus interface AC timing specifications for the configuration as
shown in Figure 13, assuming the timing relationships shown in Figure 14 and the load-
ing shown in Figure 12 on page 26.
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of G
V
DD
.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the ris-
ing or falling edge of the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 14. For consistency with other
input setup time specifications, this will be treated as negative input setup time.
4. t
L3_CLK
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the PC7457 can latch an input signal that is
valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising)
edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of
L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a
purely resistive 50
load (see Figure 12 on page 26).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 14 on page 31. For consistency with
other output valid time specifications, this will be treated as negative output valid time.
7. t
L3_CLK
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
by an internal clock delayed in phase by 90
°
. Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
8. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27 for more
information.
Table 13.
L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions
(see Table 3 on page 12)
Symbol
Parameter
All Speed Grades
Unit
Min
Max
t
L3CR
, t
L3CF
L3_CLK rise and fall time
(1)
–
0.75
ns
t
L3DVEH
, t
L3DVEL
Setup times: Data and parity
(2)(3)(4)
-0.35
–
ns
t
L3DXEH
, t
L3DXEL
Input hold times: Data and parity
(2)(4)
2.1
–
ns
t
L3CHDV
, t
L3CLDV
Valid times: Data and parity
(5)(6)(7)(8)
–
(-t
L3CLK
/4) + 0.60
ns
t
L3CHOV
Valid times: All other outputs
(5)(7)(8)
–
(t
L3CLK
/4) + 0.65
ns
t
L3CHDX
, t
L3CLDX
Output hold times: Data and parity
(5)(6)(7)(8)
(t
L3CLK
/4) - 0.60
–
ns
t
L3CHOX
Output hold times: All other outputs
(5)(7)(8)
(t
L3CLK
/4) - 0.50
–
ns
t
L3CLDZ
L3_CLK to high impedance: Data and parity
–
TBD
ns
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