參數(shù)資料
型號(hào)： PC7457VGU933N
廠商： Atmel Corp.
英文描述： PowerPC 7457 RISC Microprocessor
中文描述： 7457的PowerPC RISC微處理器
文件頁(yè)數(shù)： 57/66頁(yè)
文件大?。?/td> 522K
代理商： PC7457VGU933N
57
PC7457/47 [Preliminary]
5345B–HIREL–02/04
JTAG Configuration
Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal
is optional in the IEEE 1149.1 specification, but is provided on all processors that imple-
ment the PowerPC architecture. While it is possible to force the TAP controller to the
reset state using only the TCK and TMS signals, more reliable power-on reset perfor-
mance will be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP)
function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the
processor. If the target system has independent reset sources, such as voltage moni-
tors, watchdog timers, power supply failures, or push-button switches, then the COP
reset signals must be merged into these signals with logic.
The arrangement shown in Figure 31 allows the COP port to independently assert
HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG
interface and COP header will not be used, TRST should be tied to HRESET through a
0
isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initialized during power-on. While Motor-
ola recommends that the COP header be designed into the system as shown in Figure
31 on page 54, if this is not possible, the isolation resistor will allow future access to
TRST in the case where a JTAG interface may need to be wired onto the system in
debug situations.
The COP header shown in Figure 31 adds many benefits – breakpoints, watchpoints,
register and memory examination/modification, and other standard debugger features
are possible through this interface – and can be as inexpensive as an unpopulated foot-
print for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on
the 0.025" square-post, 0.100" centered header assembly (often called a Berg header).
The connector typically has pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 31; conse-
quently, many different pin numbers have been observed from emulator vendors. Some
are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-
bottom, while still others number the pins counter clockwise from pin 1 (as with an IC).
Regardless of the numbering, the signal placement recommended in Figure 31 is com-
mon to all known emulators.
The QACK signal shown in Figure 31 is usually connected to the PCI bridge chip in a
system and is an input to the PC7457 informing it that it can go into the quiescent state.
Under normal operation this occurs during a low-power mode selection. In order for
COP to work, the PC7457 must see this signal asserted (pulled down). While shown on
the COP header, not all emulator products drive this signal. If the product does not, a
pull-down resistor can be populated to assert this signal. Additionally, some emulator
products implement open-drain type outputs and can only drive QACK asserted; for
these tools, a pull-up resistor can be implemented to ensure this signal is deasserted
when it is not being driven by the tool. Note that the pull-up and pull-down resistors on
the QACK signal are mutually exclusive and it is never necessary to populate both in a
system. To preserve correct power-down operation, QACK should be merged via logic
so that it also can be driven by the PCI bridge.
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