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參數(shù)資料
| 型號： | PC745 |
| 英文描述： | PC755/745 Preliminary [Updated 06/03. 50 Pages] |
| 中文描述： | PC755/745初步[更新06/03。 50頁] |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC745 |
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PC755B/745B
17/48
Figure 5 shows the allowable undershoot and overshoot voltage on the PC755B and PC745B
(L2) OVdd +20%
(L2) OVdd +5%
(L2) OVdd
Gnd - 1.0V
Gnd - 0.3V
Gnd
V
IH
Not to exceed 10%
of t
SYSCLK
V
IL
Figure 5 : Overshoot/Undershoot Voltage
The PC755B provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The
PC755B core voltage must always be provided at nominal 2.0V (see Table 5 for actual recommended core voltage). Voltage to the L2
I/Os and Processor Interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in
Table 4. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL
during operation. These signals must remain stable during part operation and cannot change. The output voltage will swing from GND
to the maximum voltage applied to the OVdd or L2OVdd power pins.
Table 4 describes the input threshold voltage setting
.
Table 4. Input Threshold Voltage Setting
BVSEL Signal
L2VSEL Signal
Processor Bus Interface
Voltage
L2 Bus
Interface Voltage
0
0
1.8V or 2.0V
1.8V or 2.0V
0
1
1.8V or 2.0V
3.3V
1
0
3.3V
1.8V or 2.0V
1
1
3.3V
3.3V
Note
Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied.
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