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| 型號： | PC745 |
| 英文描述： | PC755/745 Preliminary [Updated 06/03. 50 Pages] |
| 中文描述： | PC755/745初步[更新06/03。 50頁] |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC745 |
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PC755B/745B
4. ELECTRICAL CHARACTERISTICS
4.1. Static characteristics
Table 9. DC Electrical Specifications
At recommended operating conditions (See Table 5)
Characteristic
NominalB
us
Voltage1
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except
SYSCLK)
1.8/2.0
V
IH
0.65 * (L2)OVdd
(L2)OVdd + 0.15
V
2,3
3.3
V
IH
2.0
(L2)OVdd + 0.3
V
2,3
Input low voltage (all inputs except
SYSCLK)
1.8/2.0
V
IL
-0.3
0.35 * (L2)OVdd
V
2
3.3
V
IL
-0.3
0.8
V
SYSCLK input high voltage
1.8/2.0
KV
IH
1.5
OVdd + 0.3
V
3.3
KV
IH
2.4
OVdd + 0.3
V
SYSCLK input low voltage
1.8/2.0
KV
IL
-0.3
0.2
V
3.3
KV
IL
-0.3
0.4
V
Input leakage current, V
in
=
L2OVdd/OVdd
I
in
—
10
μ
A
2,3
Hi-Z (off-state) leakage current, V
in
=
L2OVdd/OVdd
I
TSI
—
10
μ
A
2,3,5
Output high voltage, I
OH
=
-6
mA
1.8/2.0
V
OH
(L2)OVdd - 0.45
—
V
3.3
V
OH
2.4
—
V
Output low voltage, I
OL
=
6
mA
1.8/2.0
V
OL
—
0.45
V
3.3
V
OL
—
0.4
V
Capacitance, V
in
= 0 V, f = 1 MHz
C
in
—
5.0
pF
3,4
Notes:
1. Nominal voltages; See
Table 5
for recommended operating conditions.
2. For processor bus signals, the reference is OVdd
while L2OVdd is the reference for the L2 bus signals.
3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example, both
OVdd and Vdd vary by either +5% or -5%).
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