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參數(shù)資料
| 型號(hào)： | PC745BVZFU350LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |塑料 |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC745BVZFU350LD |
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PC755B/745B
Figure 13 provides the input/output timing diagram for the PC755B.
SYSCLK
ALL INPUTS
VM
VM = Midpoint Voltage (OVDD/2 or Vin/2)
ALL OUTPUTS
(Except TS, ABB,
ARTRY, DBB)
tKHOX
VM
TS,ABB,DBB
ARTRY
VM
tKHOZ
tKHABPZ
tKHARPZ
tKHARP
tKHOX
tKHOV
tKHOX
tKHOV
tKHOV
tKHOV
tKHOV
tIVKH
tKHOE
tIXKH
tKHOZ
Figure 13 : Input/Output Timing Diagram
4.2.3. L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2 divisor ratio. See Table 13 for example
core and L2 frequencies at various divisors. Table 13 provides the potential range of L2CLK output AC timing specifications as defined
in Figure 14.
The minimum L2CLK frequency of Table 13 is specified by the maximum delay of the internal DLL. The variable-tap DLL introduces up
to a full clock period delay in the L2CLKOUTA, L2CLKOUTB, and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is
phase aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2
frequency below this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the PC755B core
clock at the SRAMs.
The maximum L2CLK frequency shown in Table 13 is the core frequency divided by one. Very few L2 SRAM designs will be able to
operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access
to the L2 SRAMs. The maximum L2CLK frequency for any application of the PC755B will be a function of the AC timings of the
PC755B, the AC timings for the SRAM, bus loading, and printed circuit board trace length.
Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester
at the maximum frequencies of Table 13. Therefore functional operation and AC timing information are tested at core-to-L2 divisors of
2 or greater. Functionality of core-to-L2 divisors of 1 or 1.5 is verified at less than maximum rated frequencies.
L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core
frequency and divided down to the L2CLK frequency). In other words, the AC timings of Table 14 and Table 15 are entirely indepen-
dent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN
only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However,
since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Table 14 and Table 15 are
referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually
measured relative to SYSCLK.
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN input of the
PC755B to synchronize L2CLKOUT at the SRAM with the processor’s internal clock. L2CLKOUT at the SRAM can be offset forward
or backward in time by shortening or lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See Motorola Application Note
AN179/D “PowerPC
Backside L2 Timing Analysis for the PCB Design Engineer.”
The L2CLKOUTA and L2CLKOUTB signals should not have more than two loads.
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