參數(shù)資料
型號(hào)： PC745BVZFU350LD
英文描述： MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|PLASTIC
中文描述： 微處理器| 32位|的CMOS | BGA封裝| 255PIN |塑料
文件頁(yè)數(shù)： 42/48頁(yè)
文件大?。?/td> 276K
代理商： PC745BVZFU350LD
42/48
PC755B/745B
The PC755B generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the PC755B.
The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the PC755B to
the external RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to
the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the
internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally, the divisor must be
chosen according to the frequency supported by the external RAMs, the frequency of the PC755B core, and the phase adjustment
range that the L2 DLL supports. Figure 18 shows various example L2 clock frequencies that can be obtained for a given set of core
frequencies. The minimum L2 frequency target is 80MHz.
Table 18. Sample Core-to-L2 Frequencies
Core Frequency in MHz
1
1.5
2
2.5
3
250
250
166
125
100
83
266
266
177
133
106
89
275
275
183
138
92
300
300
200
150
120
100
325
325
217
163
130
108
333
333
222
167
133
111
350
350
233
175
140
117
366
366
244
183
146
122
375
375
250
188
150
125
400
400
266
200
160
133
Note :
The core and L2 frequencies are for reference only. Some examples may represent core
or L2 frequencies which are not useful, not supported, or not tested for by the PC755B;
see Section 4.2.1., “ L2 Clock AC Specifications,” for valid L2CLK frequencies. The
L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz.
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