45
PC755/745
2138D–HIREL–06/03
The circuit should be placed as close as possible to the AV
DD
pin to minimize noise cou-
pled from nearby circuits. An identical but separate circuit should be placed as close as
possible to the L2AV
DD
pin. It is often possible to route directly from the capacitors to the
AV
DD
pin, which is on the periphery of the 360 BGA footprint, without the inductance of
vias. The L2AV
DD
pin may be more difficult to route but is proportionately less critical.
Figure 30.
PLL Power Supply Filter Circuit
Power Supply Voltage
Sequencing
The notes in Figure 32 contain cautions about the sequencing of the external bus volt-
ages and core voltage of the PC755 (when they are different). These cautions are
necessary for the long term reliability of the part. If they are violated, the ESD (Electro-
static Discharge) protection diodes will be forward biased and excessive current can
flow through these diodes. If the system power supply design does not control the volt-
age sequencing, the circuit of Figure 32 can be added to meet these requirements. The
MUR420 Schottky diodes of Figure 32 control the maximum potential difference
between the external bus and core power supplies on power-up and the 1N5820 diodes
regulate the maximum potential difference on power-down.
Figure 31.
Example Voltage Sequencing Circuit
Decoupling
Recommendations
Due to the PC755’s dynamic power management feature, large address and data
buses, and high operating frequencies, the PC755 can generate transient power surges
and high frequency noise in its power supply, especially while driving large capacitive
loads. This noise must be prevented from reaching other components in the PC755 sys-
tem, and the PC755 itself requires a clean, tightly regulated source of power. Therefore,
it is recommended that the system designer place at least one decoupling capacitor at
each
V
DD
, O
V
DD
, and L2OV
DD
pin of the PC755. It is also recommended that these
decoupling capacitors receive their power from separate
V
DD
, (L2)OV
DD
and GND power
planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 μF or 0.1 μF. Only ceramic SMT (surface
mount technology) capacitors should be used to minimize lead inductance, preferably
0508 or 0603 orientations where connections are made along the length of the part.
V
DD
AV
DD
(or L2AV
DD
)
10
2.2 μF
2.2 μF
GND
Low ESL Surface Mount Capacitors
3.3V
2.0V
MURS320
1N5820
MURS320
1N5820