參數(shù)資料
型號: PC755CVGSU350LE
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: PowerPC 755/745 RISC Microprocessor
中文描述: 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360
封裝: SOLDER COLUMN INTERPOSER, CERAMIC, BGA-360
文件頁數(shù): 30/50頁
文件大小: 1064K
代理商: PC755CVGSU350LE
30
PC755/745
2138D–HIREL–06/03
The L2CLK_OUT timing diagram is shown in Figure 14.
Figure 14.
L2CLK_OUT Output Timing Diagram
L2 Single-Ended Clock Mode
L2 Bus Input AC Specifications
Table 16 provides the L2 bus interface AC timing specifications for the PC755 as
defined in Figure 15 and Figure 16 for the loading conditions described in Figure 17.
Table 16.
L2 Bus Interface AC Timing Specifications at Recommended Operating Conditions
VM = Midpoint Voltage (L2OVdd/2)
L2CLK_OUTA
L2CLK_OUTB
L2 Differential Clock Mode
L2SYNC_OUT
L2CLK_OUTA
VM
tL2CR
tL2CF
VM
VM
VM
L2CLK_OUTB
VM
VM
VM
VM
VM
L2SYNC_OUT
VM
VM
VM
VM
VM
VM
VM
VM
tL2CSKW
tL2CLK
tL2CLK
t
CHCL
t
CHCL
Parameter
Symbol
All Speed Grades
Unit
Min
Max
L2SYNC_IN rise and Fall Time
(1)
t
L2CR
& t
L2CF
1.0
ns
Setup Times: Data and Parity
(2)
t
DVL2CH
1.2
-
ns
Input Hold Times: Data and Parity
(2)
t
DXL2CH
0
-
ns
Valid Times:
(3)(4)
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
t
L2CHOV
-
-
-
-
3.1
3.2
3.3
3.7
ns
Output Hold Times:
(3)
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
t
L2CHOX
0.5
0.7
0.9
1.1
-
-
-
-
ns
L2SYNC_IN to High Impedance:
(3)(5)
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
t
L2CHOZ
-
-
-
-
2.4
2.6
2.8
3.0
ns
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